Changes in kernel/arch/ia32/src/smp/apic.c [84afc7b:acc7ce4] in mainline

File:

• kernel/arch/ia32/src/smp/apic.c (modified) (37 diffs)

kernel/arch/ia32/src/smp/apic.c

@@ -33 +33 @@
  */
 
-#include <arch/types.h>
+#include <typedefs.h>
 #include <arch/smp/apic.h>
 #include <arch/smp/ap.h>
@@ -53 +53 @@
  * Advanced Programmable Interrupt Controller for SMP systems.
  * Tested on:
- *      Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
- *      Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
- *      VMware Workstation 5.5 with 2 CPUs
- *      QEMU 0.8.0 with 2-15 CPUs
- *      ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
- *      ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
- *      MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
+ *    Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
+ *    Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
+ *    VMware Workstation 5.5 with 2 CPUs
+ *    QEMU 0.8.0 with 2-15 CPUs
+ *    ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
+ *    ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
+ *    MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
+ *
  */
 
@@ -69 +70 @@
  * optimize the code too much and accesses to l_apic and io_apic, that must
  * always be 32-bit, would use byte oriented instructions.
- */
-volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
-volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
+ *
+ */
+volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000);
+volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000);
 
 uint32_t apic_id_mask = 0;
+uint8_t bsp_l_apic = 0;
+
 static irq_t l_apic_timer_irq;
 
@@ -79 +83 @@
 
 #ifdef LAPIC_VERBOSE
-static char *delmod_str[] = {
+static const char *delmod_str[] = {
         "Fixed",
         "Lowest Priority",
@@ -90 +94 @@
 };
 
-static char *destmod_str[] = {
+static const char *destmod_str[] = {
         "Physical",
         "Logical"
 };
 
-static char *trigmod_str[] = {
+static const char *trigmod_str[] = {
         "Edge",
         "Level"
 };
 
-static char *mask_str[] = {
+static const char *mask_str[] = {
         "Unmasked",
         "Masked"
 };
 
-static char *delivs_str[] = {
+static const char *delivs_str[] = {
         "Idle",
         "Send Pending"
 };
 
-static char *tm_mode_str[] = {
+static const char *tm_mode_str[] = {
         "One-shot",
         "Periodic"
 };
 
-static char *intpol_str[] = {
+static const char *intpol_str[] = {
         "Polarity High",
         "Polarity Low"
@@ -123 +127 @@
 /** APIC spurious interrupt handler.
  *
- * @param n Interrupt vector.
+ * @param n      Interrupt vector.
  * @param istate Interrupted state.
- */
-static void apic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused)))
+ *
+ */
+static void apic_spurious(unsigned int n __attribute__((unused)),
+    istate_t *istate __attribute__((unused)))
 {
 #ifdef CONFIG_DEBUG
@@ -145 +151 @@
          * irq->lock so we just unlock it and then lock it again.
          */
-        spinlock_unlock(&irq->lock);
+        irq_spinlock_unlock(&irq->lock, false);
         clock();
-        spinlock_lock(&irq->lock);
+        irq_spinlock_lock(&irq->lock, false);
+}
+
+/** Get Local APIC ID.
+ *
+ * @return Local APIC ID.
+ *
+ */
+static uint8_t l_apic_id(void)
+{
+        l_apic_id_t idreg;
+        
+        idreg.value = l_apic[L_APIC_ID];
+        return idreg.apic_id;
 }
 
@@ -153 +172 @@
 void apic_init(void)
 {
-        io_apic_id_t idreg;
-        
-        exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
-
+        exc_register(VECTOR_APIC_SPUR, "apic_spurious", false,
+            (iroutine_t) apic_spurious);
+        
         enable_irqs_function = io_apic_enable_irqs;
         disable_irqs_function = io_apic_disable_irqs;
         eoi_function = l_apic_eoi;
+        irqs_info = "apic";
         
         /*
@@ -166 +185 @@
          * Other interrupts will be forwarded to the lowest priority CPU.
          */
-        io_apic_disable_irqs(0xffff);
+        io_apic_disable_irqs(0xffffU);
         
         irq_initialize(&l_apic_timer_irq);
@@ -179 +198 @@
         for (i = 0; i < IRQ_COUNT; i++) {
                 int pin;
-        
+                
                 if ((pin = smp_irq_to_pin(i)) != -1)
                         io_apic_change_ioredtbl((uint8_t) pin, DEST_ALL, (uint8_t) (IVT_IRQBASE + i), LOPRI);
@@ -187 +206 @@
          * Ensure that io_apic has unique ID.
          */
+        io_apic_id_t idreg;
+        
         idreg.value = io_apic_read(IOAPICID);
-        if ((1 << idreg.apic_id) & apic_id_mask) {      /* see if IO APIC ID is used already */
+        if ((1 << idreg.apic_id) & apic_id_mask) {  /* See if IO APIC ID is used already */
                 for (i = 0; i < APIC_ID_COUNT; i++) {
                         if (!((1 << i) & apic_id_mask)) {
@@ -197 +218 @@
                 }
         }
-
+        
         /*
          * Configure the BSP's lapic.
          */
         l_apic_init();
-
-        l_apic_debug(); 
+        l_apic_debug();
+        
+        bsp_l_apic = l_apic_id();
 }
 
@@ -211 +233 @@
  *
  * @return 0 on error, 1 on success.
+ *
  */
 int apic_poll_errors(void)
@@ -232 +255 @@
         if (esr.illegal_register_address)
                 printf("Illegal Register Address\n");
-
+        
         return !esr.err_bitmap;
 }
@@ -241 +264 @@
  *
  * @return 0 on failure, 1 on success.
+ *
  */
 int l_apic_broadcast_custom_ipi(uint8_t vector)
 {
         icr_t icr;
-
+        
         icr.lo = l_apic[ICRlo];
         icr.delmod = DELMOD_FIXED;
@@ -253 +277 @@
         icr.trigger_mode = TRIGMOD_LEVEL;
         icr.vector = vector;
-
+        
         l_apic[ICRlo] = icr.lo;
-
+        
         icr.lo = l_apic[ICRlo];
         if (icr.delivs == DELIVS_PENDING) {
@@ -262 +286 @@
 #endif
         }
-
+        
         return apic_poll_errors();
 }
@@ -271 +295 @@
  *
  * @return 0 on failure, 1 on success.
+ *
  */
 int l_apic_send_init_ipi(uint8_t apicid)
 {
+        /*
+         * Read the ICR register in and zero all non-reserved fields.
+         */
         icr_t icr;
-        int i;
-
-        /*
-         * Read the ICR register in and zero all non-reserved fields.
-         */
+        
         icr.lo = l_apic[ICRlo];
         icr.hi = l_apic[ICRhi];
@@ -293 +317 @@
         l_apic[ICRhi] = icr.hi;
         l_apic[ICRlo] = icr.lo;
-
+        
         /*
          * According to MP Specification, 20us should be enough to
@@ -299 +323 @@
          */
         delay(20);
-
+        
         if (!apic_poll_errors())
                 return 0;
-
+        
         icr.lo = l_apic[ICRlo];
         if (icr.delivs == DELIVS_PENDING) {
@@ -309 +333 @@
 #endif
         }
-
+        
         icr.delmod = DELMOD_INIT;
         icr.destmod = DESTMOD_PHYS;
@@ -317 +341 @@
         icr.vector = 0;
         l_apic[ICRlo] = icr.lo;
-
+        
         /*
          * Wait 10ms as MP Specification specifies.
          */
         delay(10000);
-
+        
         if (!is_82489DX_apic(l_apic[LAVR])) {
                 /*
                  * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
                  */
-                for (i = 0; i<2; i++) {
+                unsigned int i;
+                for (i = 0; i < 2; i++) {
                         icr.lo = l_apic[ICRlo];
                         icr.vector = (uint8_t) (((uintptr_t) ap_boot) >> 12); /* calculate the reset vector */
@@ -346 +371 @@
 void l_apic_init(void)
 {
+        /* Initialize LVT Error register. */
         lvt_error_t error;
-        lvt_lint_t lint;
-        tpr_t tpr;
-        svr_t svr;
-        icr_t icr;
-        tdcr_t tdcr;
-        lvt_tm_t tm;
-        ldr_t ldr;
-        dfr_t dfr;
-        uint32_t t1, t2;
-
-        /* Initialize LVT Error register. */
+        
         error.value = l_apic[LVT_Err];
         error.masked = true;
         l_apic[LVT_Err] = error.value;
-
+        
         /* Initialize LVT LINT0 register. */
+        lvt_lint_t lint;
+        
         lint.value = l_apic[LVT_LINT0];
         lint.masked = true;
         l_apic[LVT_LINT0] = lint.value;
-
+        
         /* Initialize LVT LINT1 register. */
         lint.value = l_apic[LVT_LINT1];
         lint.masked = true;
         l_apic[LVT_LINT1] = lint.value;
-
+        
         /* Task Priority Register initialization. */
+        tpr_t tpr;
+        
         tpr.value = l_apic[TPR];
         tpr.pri_sc = 0;
@@ -379 +399 @@
         
         /* Spurious-Interrupt Vector Register initialization. */
+        svr_t svr;
+        
         svr.value = l_apic[SVR];
         svr.vector = VECTOR_APIC_SPUR;
@@ -384 +406 @@
         svr.focus_checking = true;
         l_apic[SVR] = svr.value;
-
+        
         if (CPU->arch.family >= 6)
                 enable_l_apic_in_msr();
         
         /* Interrupt Command Register initialization. */
+        icr_t icr;
+        
         icr.lo = l_apic[ICRlo];
         icr.delmod = DELMOD_INIT;
@@ -398 +422 @@
         
         /* Timer Divide Configuration Register initialization. */
+        tdcr_t tdcr;
+        
         tdcr.value = l_apic[TDCR];
         tdcr.div_value = DIVIDE_1;
         l_apic[TDCR] = tdcr.value;
-
+        
         /* Program local timer. */
+        lvt_tm_t tm;
+        
         tm.value = l_apic[LVT_Tm];
         tm.vector = VECTOR_CLK;
@@ -408 +436 @@
         tm.masked = false;
         l_apic[LVT_Tm] = tm.value;
-
+        
         /*
          * Measure and configure the timer to generate timer
          * interrupt with period 1s/HZ seconds.
          */
+        uint32_t t1 = l_apic[CCRT];
+        l_apic[ICRT] = 0xffffffff;
+        
+        while (l_apic[CCRT] == t1);
+        
         t1 = l_apic[CCRT];
-        l_apic[ICRT] = 0xffffffff;
-
-        while (l_apic[CCRT] == t1)
-                ;
-                
-        t1 = l_apic[CCRT];
-        delay(1000000/HZ);
-        t2 = l_apic[CCRT];
-        
-        l_apic[ICRT] = t1-t2;
+        delay(1000000 / HZ);
+        uint32_t t2 = l_apic[CCRT];
+        
+        l_apic[ICRT] = t1 - t2;
         
         /* Program Logical Destination Register. */
-        ASSERT(CPU->id < 8)
+        ASSERT(CPU->id < 8);
+        ldr_t ldr;
+        
         ldr.value = l_apic[LDR];
         ldr.id = (uint8_t) (1 << CPU->id);
@@ -432 +461 @@
         
         /* Program Destination Format Register for Flat mode. */
+        dfr_t dfr;
+        
         dfr.value = l_apic[DFR];
         dfr.model = MODEL_FLAT;
@@ -447 +478 @@
 {
 #ifdef LAPIC_VERBOSE
+        printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
+            CPU->id, l_apic_id());
+        
         lvt_tm_t tm;
+        tm.value = l_apic[LVT_Tm];
+        printf("LVT Tm: vector=%" PRIu8 ", %s, %s, %s\n",
+            tm.vector, delivs_str[tm.delivs], mask_str[tm.masked],
+            tm_mode_str[tm.mode]);
+        
         lvt_lint_t lint;
-        lvt_error_t error;      
-        
-        printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
-
-        tm.value = l_apic[LVT_Tm];
-        printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
         lint.value = l_apic[LVT_LINT0];
-        printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
-        lint.value = l_apic[LVT_LINT1]; 
-        printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);  
+        printf("LVT LINT0: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
+            tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs],
+            intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
+            mask_str[lint.masked]);
+        
+        lint.value = l_apic[LVT_LINT1];
+        printf("LVT LINT1: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
+            tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs],
+            intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
+            mask_str[lint.masked]);
+        
+        lvt_error_t error;
         error.value = l_apic[LVT_Err];
-        printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
+        printf("LVT Err: vector=%" PRIu8 ", %s, %s\n", error.vector,
+            delivs_str[error.delivs], mask_str[error.masked]);
 #endif
 }
 
-/** Get Local APIC ID.
- *
- * @return Local APIC ID.
- */
-uint8_t l_apic_id(void)
-{
-        l_apic_id_t idreg;
-        
-        idreg.value = l_apic[L_APIC_ID];
-        return idreg.apic_id;
-}
-
 /** Read from IO APIC register.
  *
@@ -481 +512 @@
  *
  * @return Content of the addressed IO APIC register.
+ *
  */
 uint32_t io_apic_read(uint8_t address)
@@ -495 +527 @@
  *
  * @param address IO APIC register address.
- * @param x Content to be written to the addressed IO APIC register.
- */
-void io_apic_write(uint8_t address, uint32_t x)
+ * @param val     Content to be written to the addressed IO APIC register.
+ *
+ */
+void io_apic_write(uint8_t address, uint32_t val)
 {
         io_regsel_t regsel;
@@ -504 +537 @@
         regsel.reg_addr = address;
         io_apic[IOREGSEL] = regsel.value;
-        io_apic[IOWIN] = x;
+        io_apic[IOWIN] = val;
 }
 
 /** Change some attributes of one item in I/O Redirection Table.
  *
- * @param pin IO APIC pin number.
- * @param dest Interrupt destination address.
- * @param v Interrupt vector to trigger.
+ * @param pin   IO APIC pin number.
+ * @param dest  Interrupt destination address.
+ * @param vec   Interrupt vector to trigger.
  * @param flags Flags.
- */
-void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags)
-{
-        io_redirection_reg_t reg;
-        int dlvr = DELMOD_FIXED;
+ *
+ */
+void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t vec,
+    unsigned int flags)
+{
+        unsigned int dlvr;
         
         if (flags & LOPRI)
                 dlvr = DELMOD_LOWPRI;
-
+        else
+                dlvr = DELMOD_FIXED;
+        
+        io_redirection_reg_t reg;
         reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
         reg.hi = io_apic_read((uint8_t) (IOREDTBL + pin * 2 + 1));
@@ -530 +567 @@
         reg.intpol = POLARITY_HIGH;
         reg.delmod = dlvr;
-        reg.intvec = v;
-
+        reg.intvec = vec;
+        
         io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
         io_apic_write((uint8_t) (IOREDTBL + pin * 2 + 1), reg.hi);
@@ -539 +576 @@
  *
  * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
+ *
  */
 void io_apic_disable_irqs(uint16_t irqmask)
 {
-        io_redirection_reg_t reg;
         unsigned int i;
-        int pin;
-        
         for (i = 0; i < 16; i++) {
                 if (irqmask & (1 << i)) {
@@ -552 +587 @@
                          * mapping for the respective IRQ number.
                          */
-                        pin = smp_irq_to_pin(i);
+                        int pin = smp_irq_to_pin(i);
                         if (pin != -1) {
+                                io_redirection_reg_t reg;
+                                
                                 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
                                 reg.masked = true;
@@ -566 +603 @@
  *
  * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
+ *
  */
 void io_apic_enable_irqs(uint16_t irqmask)
 {
         unsigned int i;
-        int pin;
-        io_redirection_reg_t reg;       
-        
         for (i = 0; i < 16; i++) {
                 if (irqmask & (1 << i)) {
@@ -579 +614 @@
                          * mapping for the respective IRQ number.
                          */
-                        pin = smp_irq_to_pin(i);
+                        int pin = smp_irq_to_pin(i);
                         if (pin != -1) {
+                                io_redirection_reg_t reg;
+                                
                                 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
                                 reg.masked = false;