Changeset ad6857c in mainline for uspace/drv/pciintel/pci.c

Timestamp:

2011-02-27T02:43:29Z (14 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8e1eb4d0

Parents:

1ae51ae

Message:

Fixed: pciintel reports correct io sizes

BIG FAT WARNING!!!:
I don't know whether the new version is correct, but it gets correct
values for my nb with intel chipset (as far as I can tell).
Someone with actual knowledge about PCI bus should definitely look at this.

File:

• uspace/drv/pciintel/pci.c (modified) (3 diffs)

uspace/drv/pciintel/pci.c

@@ -320 +320 @@
         /* Get the value of the BAR. */
         val = pci_conf_read_32(fun, addr);
+
+#define IO_MASK  (~0x3)
+#define MEM_MASK (~0xf)
         
         io = (bool) (val & 1);
         if (io) {
                 addrw64 = false;
+                mask = IO_MASK;
         } else {
+                mask = MEM_MASK;
                 switch ((val >> 1) & 3) {
                 case 0:
@@ -340 +345 @@
         /* Get the address mask. */
         pci_conf_write_32(fun, addr, 0xffffffff);
-        mask = pci_conf_read_32(fun, addr);
+        mask &= pci_conf_read_32(fun, addr);
         
         /* Restore the original value. */
@@ -659 +664 @@
 size_t pci_bar_mask_to_size(uint32_t mask)
 {
-        return ((mask & 0xfffffff0) ^ 0xffffffff) + 1;
+        size_t size = mask & ~(mask - 1);
+        return size;
 }