Changeset aecf79f in mainline for kernel/arch/xen32/src/pm.c

Timestamp:

2006-07-24T16:07:15Z (18 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

c59dd1a2

Parents:

7b0599b

Message:

xen memory initialization

File:

• kernel/arch/xen32/src/pm.c (modified) (6 diffs)

kernel/arch/xen32/src/pm.c

@@ -74 +74 @@
         /* TLS descriptor */
         { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
-        /* VESA Init descriptor */
-#ifdef CONFIG_FB
-        { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
-#endif  
 };
 
@@ -153 +149 @@
 static void clean_IOPL_NT_flags(void)
 {
-        __asm__ volatile (
-                "pushfl\n"
-                "pop %%eax\n"
-                "and $0xffff8fff, %%eax\n"
-                "push %%eax\n"
-                "popfl\n"
-                : : : "eax"
-        );
+//      __asm__ volatile (
+//              "pushfl\n"
+//              "pop %%eax\n"
+//              "and $0xffff8fff, %%eax\n"
+//              "push %%eax\n"
+//              "popfl\n"
+//              : : : "eax"
+//      );
 }
 
@@ -166 +162 @@
 static void clean_AM_flag(void)
 {
-        __asm__ volatile (
-                "mov %%cr0, %%eax\n"
-                "and $0xfffbffff, %%eax\n"
-                "mov %%eax, %%cr0\n"
-                : : : "eax"
-        );
+//      __asm__ volatile (
+//              "mov %%cr0, %%eax\n"
+//              "and $0xfffbffff, %%eax\n"
+//              "mov %%eax, %%cr0\n"
+//              : : : "eax"
+//      );
 }
 
@@ -184 +180 @@
         idtr.limit = sizeof(idt);
         idtr.base = (uintptr_t) idt;
-        gdtr_load(&gdtr);
-        idtr_load(&idtr);
+//      gdtr_load(&gdtr);
+//      idtr_load(&idtr);
         
         /*
@@ -192 +188 @@
          */
 
-        if (config.cpu_active == 1) {
-                idt_init();
-                /*
-                 * NOTE: bootstrap CPU has statically allocated TSS, because
-                 * the heap hasn't been initialized so far.
-                 */
+//      if (config.cpu_active == 1) {
+//              idt_init();
+//              /*
+//               * NOTE: bootstrap CPU has statically allocated TSS, because
+//               * the heap hasn't been initialized so far.
+//               */
                 tss_p = &tss;
-        }
-        else {
-                tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
-                if (!tss_p)
-                        panic("could not allocate TSS\n");
-        }
-
-        tss_initialize(tss_p);
+//      }
+//      else {
+//              tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
+//              if (!tss_p)
+//                      panic("could not allocate TSS\n");
+//      }
+
+//      tss_initialize(tss_p);
         
         gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
@@ -219 +215 @@
          * to its own TSS. We just need to load the TR register.
          */
-        tr_load(selector(TSS_DES));
+//      tr_load(selector(TSS_DES));
         
         clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */