Changes in uspace/drv/pciintel/pci.c [40a5d40:af6b5157] in mainline
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uspace/drv/pciintel/pci.c
r40a5d40 raf6b5157 51 51 #include <ipc/devman.h> 52 52 #include <ipc/dev_iface.h> 53 #include <ipc/irc.h>54 #include <ipc/ns.h>55 #include <ipc/services.h>56 #include <sysinfo.h>57 53 #include <ops/hw_res.h> 58 54 #include <device/hw_res.h> 59 55 #include <ddi.h> 60 56 #include <libarch/ddi.h> 61 #include <pci_dev_iface.h>62 57 63 58 #include "pci.h" … … 88 83 static bool pciintel_enable_interrupt(ddf_fun_t *fnode) 89 84 { 90 /* This is an old ugly way, copied from ne2000 driver */ 91 assert(fnode); 92 pci_fun_t *dev_data = (pci_fun_t *) fnode->driver_data; 93 94 sysarg_t apic; 95 sysarg_t i8259; 96 97 int irc_phone = -1; 98 int irc_service = 0; 99 100 if ((sysinfo_get_value("apic", &apic) == EOK) && (apic)) { 101 irc_service = SERVICE_APIC; 102 } else if ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259)) { 103 irc_service = SERVICE_I8259; 104 } 105 106 if (irc_service == 0) 107 return false; 108 109 irc_phone = service_connect_blocking(irc_service, 0, 0); 110 if (irc_phone < 0) 111 return false; 112 113 size_t i; 114 for (i = 0; i < dev_data->hw_resources.count; i++) { 115 if (dev_data->hw_resources.resources[i].type == INTERRUPT) { 116 int irq = dev_data->hw_resources.resources[i].res.interrupt.irq; 117 int rc = async_req_1_0(irc_phone, IRC_ENABLE_INTERRUPT, irq); 118 if (rc != EOK) { 119 async_hangup(irc_phone); 120 return false; 121 } 122 } 123 } 124 125 async_hangup(irc_phone); 126 return true; 127 } 128 129 static int pci_config_space_write_32( 130 ddf_fun_t *fun, uint32_t address, uint32_t data) 131 { 132 if (address > 252) 133 return EINVAL; 134 pci_conf_write_32(PCI_FUN(fun), address, data); 135 return EOK; 136 } 137 138 static int pci_config_space_write_16( 139 ddf_fun_t *fun, uint32_t address, uint16_t data) 140 { 141 if (address > 254) 142 return EINVAL; 143 pci_conf_write_16(PCI_FUN(fun), address, data); 144 return EOK; 145 } 146 147 static int pci_config_space_write_8( 148 ddf_fun_t *fun, uint32_t address, uint8_t data) 149 { 150 if (address > 255) 151 return EINVAL; 152 pci_conf_write_8(PCI_FUN(fun), address, data); 153 return EOK; 154 } 155 156 static int pci_config_space_read_32( 157 ddf_fun_t *fun, uint32_t address, uint32_t *data) 158 { 159 if (address > 252) 160 return EINVAL; 161 *data = pci_conf_read_32(PCI_FUN(fun), address); 162 return EOK; 163 } 164 165 static int pci_config_space_read_16( 166 ddf_fun_t *fun, uint32_t address, uint16_t *data) 167 { 168 if (address > 254) 169 return EINVAL; 170 *data = pci_conf_read_16(PCI_FUN(fun), address); 171 return EOK; 172 } 173 174 static int pci_config_space_read_8( 175 ddf_fun_t *fun, uint32_t address, uint8_t *data) 176 { 177 if (address > 255) 178 return EINVAL; 179 *data = pci_conf_read_8(PCI_FUN(fun), address); 180 return EOK; 85 /* TODO */ 86 87 return false; 181 88 } 182 89 … … 186 93 }; 187 94 188 static pci_dev_iface_t pci_dev_ops = { 189 .config_space_read_8 = &pci_config_space_read_8, 190 .config_space_read_16 = &pci_config_space_read_16, 191 .config_space_read_32 = &pci_config_space_read_32, 192 .config_space_write_8 = &pci_config_space_write_8, 193 .config_space_write_16 = &pci_config_space_write_16, 194 .config_space_write_32 = &pci_config_space_write_32 195 }; 196 197 static ddf_dev_ops_t pci_fun_ops = { 198 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops, 199 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops 200 }; 95 static ddf_dev_ops_t pci_fun_ops; 201 96 202 97 static int pci_add_device(ddf_dev_t *); … … 392 287 /* Get the value of the BAR. */ 393 288 val = pci_conf_read_32(fun, addr); 394 395 #define IO_MASK (~0x3)396 #define MEM_MASK (~0xf)397 289 398 290 io = (bool) (val & 1); 399 291 if (io) { 400 292 addrw64 = false; 401 mask = IO_MASK;402 293 } else { 403 mask = MEM_MASK;404 294 switch ((val >> 1) & 3) { 405 295 case 0: … … 417 307 /* Get the address mask. */ 418 308 pci_conf_write_32(fun, addr, 0xffffffff); 419 mask &= pci_conf_read_32(fun, addr);309 mask = pci_conf_read_32(fun, addr); 420 310 421 311 /* Restore the original value. */ … … 665 555 { 666 556 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops; 667 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;668 557 } 669 558 … … 737 626 size_t pci_bar_mask_to_size(uint32_t mask) 738 627 { 739 size_t size = mask & ~(mask - 1); 740 return size; 628 return ((mask & 0xfffffff0) ^ 0xffffffff) + 1; 741 629 } 742 630
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