Changeset b0bf501 in mainline


Ignore:
Timestamp:
2005-06-06T20:42:06Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a7a1063
Parents:
e3f41b6
Message:

Define two placeholder functions for atomic_inc and atomic_dec on IA-64.

Add Ondrej Palkovsky to doc/AUTHORS.

Tweaks in IA-32 low level code to bring SMP back to life. (SMP still broken)

Files:
9 edited

Legend:

Unmodified
Added
Removed

  • arch/ia32/src/boot/boot.S

    re3f41b6 rb0bf501  
    4848        orl $0x1,%eax
    4949        movl %eax,%cr0
    50         jmp 0f
    51 0:
     50        jmpl $8,$meeting_point
     51meeting_point:
     52.code32
     53
    5254        movw $16,%ax
    5355        movw %ax,%es
    … …  
    5759        movw %ax,%ss
    5860        movl $0x7c00,%esp
    59         jmpl $8,$meeting_point
    60 meeting_point:
    61 .code32
    6261
    6362        lidt idtr
    … …  
    9796        orl $(1<<31), %ebx
    9897        movl %ebx, %cr0
     98        jmp 0f
     990:
    99100        ret
    100101

  • arch/ia32/src/pm.c

    re3f41b6 rb0bf501  
    7272void gdt_setbase(struct descriptor *d, __address base)
    7373{
    74         d->base_0_15 = KA2PA(base) & 0xffff;
    75         d->base_16_23 = (KA2PA(base) >> 16) & 0xff;
    76         d->base_24_31 = (KA2PA(base) >> 24) & 0xff;
     74        d->base_0_15 = base & 0xffff;
     75        d->base_16_23 = ((base) >> 16) & 0xff;
     76        d->base_24_31 = ((base) >> 24) & 0xff;
    7777
    7878}
    … …  
    8686void idt_setoffset(struct idescriptor *d, __address offset)
    8787{
    88         d->offset_0_15 = KA2PA(offset) & 0xffff;
    89         d->offset_16_31 = KA2PA(offset) >> 16;
     88        /*
     89         * Offset is a linear address.
     90         */
     91        d->offset_0_15 = offset & 0xffff;
     92        d->offset_16_31 = offset >> 16;
    9093}
    9194

  • arch/ia32/src/smp/ap.S

    re3f41b6 rb0bf501  
    5555        orl $1,%eax
    5656        movl %eax,%cr0
    57         jmp 0f
    58 0:
    59         ljmp $KTEXT,$jump_to_kernel
    60 
    61 # this is where the AP enters the kernel space
     57        jmpl $KTEXT,$jump_to_kernel
    6258jump_to_kernel:
    6359.code32

  • arch/ia32/src/smp/apic.c

    re3f41b6 rb0bf501  
    4444 * Advanced Programmable Interrupt Controller for MP systems.
    4545 * Tested on:
    46  *      Bochs 2.0.2 - Bochs 2.2-cvs with 2-8 CPUs
     46 *      Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
    4747 *      ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
    4848 */

  • arch/ia64/include/atomic.h

    re3f41b6 rb0bf501  
     1/*
     2 * Copyright (C) 2005 Jakub Jermar
     3 * All rights reserved.
     4 *
     5 * Redistribution and use in source and binary forms, with or without
     6 * modification, are permitted provided that the following conditions
     7 * are met:
     8 *
     9 * - Redistributions of source code must retain the above copyright
     10 *   notice, this list of conditions and the following disclaimer.
     11 * - Redistributions in binary form must reproduce the above copyright
     12 *   notice, this list of conditions and the following disclaimer in the
     13 *   documentation and/or other materials provided with the distribution.
     14 * - The name of the author may not be used to endorse or promote products
     15 *   derived from this software without specific prior written permission.
     16 *
     17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27 */
     28
     29#ifndef __ia64_ATOMIC_H__
     30#define __ia64_ATOMIC_H__
     31
     32/*
     33 * TODO: these are just placeholders for real implementations of atomic_inc and atomic_dec.
     34 * WARNING: the following functions cause the code to be preemption-unsafe !!!
     35 */
     36
     37static inline atomic_inc(volatile int *val) {
     38        *val++;
     39}
     40
     41static inline atomic_dec(volatile int *val) {
     42        *val--;
     43}
     44
     45#endif

  • arch/mips/include/atomic.h

    re3f41b6 rb0bf501  
    11/*
    2  * Copyright (C) 2001-2004 Jakub Jermar
     2 * Copyright (C) 2005 Ondrej Palkovsky
    33 * All rights reserved.
    44 *

  • doc/AUTHORS

    re3f41b6 rb0bf501  
    44Josef Cejka
    55Sergey Bondari
     6Ondrej Palkovsky

  • doc/requirements

    re3f41b6 rb0bf501  
    1111
    1212    SMP COMPATIBILITY
    13     o Bochs 2.0.2 - Bochs 2.2-cvs
     13    o Bochs 2.0.2 - Bochs 2.2
    1414        o 2x-8x 686 CPU
    1515    o ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41

  • src/Makefile.config

    re3f41b6 rb0bf501  
    1515
    1616# Deadlock detection support for spinlocks.
    17 #DEBUG_SPINLOCK=DEBUG_SPINLOCK
     17DEBUG_SPINLOCK=DEBUG_SPINLOCK
    1818
    1919# Uncomment if you want to compile in userspace support
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