Ignore:
Timestamp:
2013-01-24T21:18:18Z (12 years ago)
Author:
Maurizio Lombardi <m.lombardi85@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
077b9172
Parents:
5e761f3 (diff), c124dce3 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge changes from jan.vesely/helenos/arm

File:
1 edited

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  • kernel/arch/arm32/include/mm/page_fault.h

    r5e761f3 rb1011dae  
    4242/** Decribes CP15 "fault status register" (FSR).
    4343 *
    44  * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743).
     44 * "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
     45 * It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
     46 * the architecture. A write flag (bit[11] of the DFSR) has also been
     47 * introduced."
     48 * ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
     49 *
     50 * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743). for FSR info
    4551 */
    4652typedef union {
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