Changeset b1cf98c in mainline
- Timestamp:
- 2005-09-13T20:02:26Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- d6dcdd2e
- Parents:
- 2e5f770
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/src/boot/boot.S
r2e5f770 rb1cf98c 56 56 xorw %ax,%ax 57 57 movw %ax,%ds 58 movw %ax,%es 58 59 movw %ax,%ss # initialize stack segment register 59 60 movl $(START_STACK), %esp # initialize stack pointer -
arch/ia32/src/acpi/acpi.c
r2e5f770 rb1cf98c 109 109 110 110 rsdp_found: 111 printf("% L: ACPI Root System Description Pointer\n", acpi_rsdp);111 printf("%P: ACPI Root System Description Pointer\n", acpi_rsdp); 112 112 113 113 acpi_rsdt = (struct acpi_rsdt *) (__native) acpi_rsdp->rsdt_address; … … 144 144 goto next; 145 145 *signature_map[j].sdt_ptr = h; 146 printf("% L: ACPI %s\n", *signature_map[j].sdt_ptr, signature_map[j].description);146 printf("%P: ACPI %s\n", *signature_map[j].sdt_ptr, signature_map[j].description); 147 147 } 148 148 } … … 165 165 goto next; 166 166 *signature_map[j].sdt_ptr = h; 167 printf("% L: ACPI %s\n", *signature_map[j].sdt_ptr, signature_map[j].description);167 printf("%P: ACPI %s\n", *signature_map[j].sdt_ptr, signature_map[j].description); 168 168 } 169 169 } -
arch/ia32/src/boot/boot.S
r2e5f770 rb1cf98c 53 53 xorw %ax, %ax 54 54 movw %ax, %ds 55 movw %ax, %es 55 56 movw %ax, %ss # initialize stack segment register 56 57 movl $BOOTSTRAP_OFFSET - 0x400, %esp # initialize stack pointer … … 86 87 movw %ax, %ss 87 88 88 movb $0xd1, %al # enable A20 using the keyboardcontroller89 movb $0xd1, %al # enable A20 using i8042 controller 89 90 outb %al, $0x64 90 91 movb $0xdf, %al -
arch/ia32/src/boot/memmap.S
r2e5f770 rb1cf98c 39 39 40 40 memmap_arch_init: 41 42 41 e820begin: 43 xorl %ebx,%ebx # during first call, ebx must be 0 44 movw %bx,%ds 45 movw %bx,%es 42 xorl %ebx,%ebx # during first call, ebx must be 0 46 43 movw $e820table_boot,%di 47 44 movb $MEMMAP_E820_MAX_RECORDS,e820counter_boot 48 45 e820loop: 49 movl $E820_SMAP,%edx # control sequence "SMAP"46 movl $E820_SMAP,%edx # control sequence "SMAP" 50 47 51 movl $0x0000e820,%eax # service48 movl $0x0000e820,%eax # service 52 49 movl $MEMMAP_E820_RECORD_SIZE,%ecx 53 50 int $0x15 54 51 jc e820err 55 52 56 cmpl $E820_SMAP,%eax # verifying BIOS53 cmpl $E820_SMAP,%eax # verifying BIOS 57 54 jne e820err 58 55 59 56 cmpl $MEMMAP_E820_RECORD_SIZE,%ecx 60 jne e820err # bad record size - bug in bios57 jne e820err # bad record size - bug in bios 61 58 62 movw %di,%ax # next record59 movw %di,%ax # next record 63 60 addw $MEMMAP_E820_RECORD_SIZE,%ax 64 61 movw %ax,%di 65 62 66 decb e820counter_boot # buffer is full63 decb e820counter_boot # buffer is full 67 64 jz e820end 68 65 69 cmpl $0,%ebx70 jn ee820loop66 testl %ebx,%ebx 67 jnz e820loop 71 68 72 69 e820end: 73 70 movb $MEMMAP_E820_MAX_RECORDS,%al 74 71 subb e820counter_boot,%al 75 movb %al,e820counter_boot # store # of valid entries in e820counter72 movb %al,e820counter_boot # store # of valid entries in e820counter 76 73 77 74 jmp e801begin … … 92 89 jc e801end 93 90 94 91 # fix problem with some BIOSes which use ax:bx rather than cx:dx 95 92 testw %cx,%cx 96 93 jnz e801cxdx … … 106 103 andl $0xffff,%ecx 107 104 addl %ecx,%edx 108 addl $0x0400,%edx # add lower 1 MB - it's not included by e801 method105 addl $0x0400,%edx # add lower 1 MB - it's not included by e801 method 109 106 movl %edx,e801memorysize 110 107 e801end: 111 108 ret 112 109 113 #memory size in 1 kb chunks 110 111 .section K_DATA_START 112 113 #memory size in 1 kb chunks 114 114 e801memorysize: 115 115 .long 0 116 -
arch/ia32/src/smp/mps.c
r2e5f770 rb1cf98c 186 186 187 187 fs_found: 188 printf("% L: MPS Floating Pointer Structure\n", fs);188 printf("%P: MPS Floating Pointer Structure\n", fs); 189 189 190 190 frame_not_free((__address) fs); … … 408 408 switch (cur[CT_EXT_ENTRY_TYPE]) { 409 409 default: 410 printf("% L: skipping MP Configuration Table extended entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]);410 printf("%P: skipping MP Configuration Table extended entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]); 411 411 break; 412 412 } -
doc/arch/amd64
r2e5f770 rb1cf98c 2 2 ========== 3 3 4 The fifth port, amd64 port, is heavily based on ia32 port. 5 It was originally written by Ondrej Palkovsky. 6 The goal is to support AMD64 or Intel Extended Memory PC's. 7 The new 64-bit code makes use of portable parts of ia32. 4 The fifth port, amd64 port, was originally written by Ondrej Palkovsky. 5 The goal is to support AMD64 and Intel Extended Memory 64 Technology PC's. 6 The port makes use of portable parts of ia32. 8 7 Both uniprocessors and multiprocessors are supported. 9 It has not been tested on real hardware, so far.8 The kernel runs on real hardware and in simulators too. 10 9 11 10 HARDWARE REQUIREMENTS 12 o no real hardware supported 11 o AMD64 architecture processor 12 o Intel Extended Memory 64 Technology processor 13 14 CPU 15 o Intel Xeon with Intel Extended Memory 64 Technology 13 16 14 17 SMP COMPATIBILITY 15 18 o Bochs 2.2.1 16 19 o 2x-8x AMD64 CPU 17 o Simics Simics2.2.1920 o Simics 2.2.19 18 21 o 2x-8x AMD hammer CPU 22 o HP ProLiant ML350 (HyperThreading) 19 23 20 24 EMULATORS AND VIRTUALIZERS 21 o Bochs 2.2 22 o Simics Simics2.2.1925 o Bochs 2.2.1 26 o Simics 2.2.19 -
doc/arch/ia32
r2e5f770 rb1cf98c 6 6 It is meant to support ordinary PC's based on IA-32 architecture. 7 7 Both uniprocessor and multiprocessor modes are supported. 8 It runs on both emulated environment andreal hardware.8 It runs both in emulated environment and on real hardware. 9 9 10 10 HARDWARE REQUIREMENTS -
doc/arch/mips32
r2e5f770 rb1cf98c 11 11 o emulated MIPS 4K CPU 12 12 13 CPU 14 o QED R4600 15 13 16 COMPILER REQUIREMENTS 14 17 o mips binutils 2.16 and gcc 4.0.1 cross compiler
Note:
See TracChangeset
for help on using the changeset viewer.