Changeset b2e5e25 in mainline

Timestamp:

2006-12-22T11:20:38Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b43eaba0

Parents:

b6e97d7

Message:

Improve comments.

Location:

kernel/arch/sparc64/src

Files:

• start.S (modified) (1 diff)
• trap/trap_table.S (modified) (1 diff)

kernel/arch/sparc64/src/start.S

@@ -330 +330 @@
  * used only for a very limited period of time, but we switch to it anyway,
  * just to be sure we are properly initialized.
- *
- * What is important is that this piece of memory is covered by the 4M DTLB
- * locked entry and therefore there will be no surprises like deadly
- * combinations of spill trap and and TLB miss on the stack address.
  */
 

kernel/arch/sparc64/src/trap/trap_table.S

@@ -630 +630 @@
  * handlers.
  *
- * This function can be entered either with interrupt globals or alternate globals.
- * Memory management trap handlers are obliged to switch to one of those global sets
- * prior to calling this function. Register window management functions are not
- * allowed to modify the alternate global registers.
+ * This function can be entered either with interrupt globals or alternate
+ * globals. Memory management trap handlers are obliged to switch to one of
+ * those global sets prior to calling this function. Register window management
+ * functions are not allowed to modify the alternate global registers.
+ *
+ * The kernel is designed to work on trap levels 0 - 4. For instance, the
+ * following can happen:
+ * TL0: kernel thread runs (CANSAVE=0, kernel stack not in DTLB)
+ * TL1: preemptible trap handler started after a tick interrupt
+ * TL2: preemptible trap handler did SAVE
+ * TL3: spill handler touched the kernel stack  
+ * TL4: hardware or software failure
  *
  * Input registers: