Changeset b3cf946 in mainline


Ignore:
Timestamp:
2013-09-03T19:29:41Z (11 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
aa2a049
Parents:
730ff63
Message:

Build uspace with sun4v specific options.

  • Optimize for Niagara.
  • Tell the compiler not to use VIS instrustion set as some of these instructions (eg. fpmerge) are not directly implemented by the Niagara CPU.
File:
1 edited

Legend:

Unmodified
Added
Removed

  • uspace/lib/c/arch/sparc64/Makefile.common

    r730ff63 rb3cf946  
    2727#
    2828
    29 GCC_CFLAGS += -mcpu=ultrasparc -m64 -mcmodel=medlow
     29ifeq ($(PROCESSOR),sun4v)
     30GCC_CFLAGS += -mcpu=niagara -mno-vis
     31else
     32GCC_CFLAGS += -mcpu=ultrasparc
     33endif
     34
     35GCC_CFLAGS += -m64 -mcmodel=medlow
     36
    3037LFLAGS = -no-check-sections
    3138
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