Changeset b3e8c90 in mainline for kernel/arch/sparc64/src/sparc64.c

Timestamp:

2006-08-01T11:24:27Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e386cbf

Parents:

c049309

Message:

sparc64 work.

1. Formatting fixes.
2. When writing to DMMU ASI's, simple membar() can be used in place of flush().
3. Substantial changes in the way the TLB is taken over.
4. Remove unneeded functions.

This is the first revision that also runs on a real world Ultra 5 with UltraSPARC IIi
processor.

Note that 3. needs further work as the current implementation depends on the fact
that the compiler will use registers for local variables in take_over_tlb_and_tt().
Rewrite of that function into assembly is to follow.

File:

• kernel/arch/sparc64/src/sparc64.c (modified) (3 diffs)

kernel/arch/sparc64/src/sparc64.c

@@ -97 +97 @@
  * trap table.
  *
- * The goal of this function is to disable MMU
- * so that both TLBs can be purged and new
- * kernel 4M locked entry can be installed.
- * After TLB is initialized, MMU is enabled
- * again.
+ * First, demap context 0 and install the
+ * global 4M locked kernel mapping.
  *
- * Switching MMU off imposes the requirement for
- * the kernel to run in identity mapped environment.
+ * Second, prepare a temporary IMMU mapping in
+ * context 1, switch to it, demap context 0,
+ * install the global 4M locked kernel mapping
+ * in context 0 and switch back to context 0.
  *
  * @param base Base address that will be hardwired in both TLBs.
@@ -115 +114 @@
         page_address_t pg;
 
+        /*
+         * Switch to the kernel trap table.
+         */
+        trap_switch_trap_table();
+
         fr.address = base;
         pg.address = base;
 
-        immu_disable();
-        dmmu_disable();
-
-        /*
-         * Demap everything, especially OpenFirmware.
-         */
-        itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
-        dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
-        
         /*
          * We do identity mapping of 4M-page at 4M.
          */
-        tag.value = ASID_KERNEL;
+        tag.value = 0;
+        tag.context = 0;
         tag.vpn = pg.vpn;
-
-        itlb_tag_access_write(tag.value);
-        dtlb_tag_access_write(tag.value);
 
         data.value = 0;
@@ -142 +135 @@
         data.l = true;
         data.cp = 1;
-        data.cv = 1;
+        data.cv = 0;
         data.p = true;
         data.w = true;
         data.g = true;
 
-        itlb_data_in_write(data.value);
+        /*
+         * Straightforwardly demap DMUU context 0,
+         * and replace it with the locked kernel mapping.
+         */
+        dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
+        dtlb_tag_access_write(tag.value);
         dtlb_data_in_write(data.value);
 
         /*
-         * Register window traps can occur before MMU is enabled again.
-         * This ensures that any such traps will be handled from 
-         * kernel identity mapped trap handler.
+         * Install kernel code mapping in context 1
+         * and switch to it.
          */
-        trap_switch_trap_table();
+        tag.context = 1;
+        data.g = false;
+        itlb_tag_access_write(tag.value);
+        itlb_data_in_write(data.value);
+        mmu_primary_context_write(1);
         
-        tlb_invalidate_all();
-
-        dmmu_enable();
-        immu_enable();
+        /*
+         * Demap old context 0.
+         */
+        itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
+        
+        /*
+         * Install the locked kernel mapping in context 0
+         * and switch to it.
+         */
+        tag.context = 0;
+        data.g = true;
+        itlb_tag_access_write(tag.value);
+        itlb_data_in_write(data.value);
+        mmu_primary_context_write(0);
 }