Changeset b5a3b50 in mainline for boot/arch/arm32/src/mm.c
- Timestamp:
- 2012-12-31T08:41:10Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 029e3cc, 17cc8f4f, 660e8fa, 664fd6d5
- Parents:
- b55877d
- git-author:
- Beniamino Galvani <b.galvani@…> (2012-12-31 08:41:10)
- git-committer:
- Jakub Jermar <jakub@…> (2012-12-31 08:41:10)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/arm32/src/mm.c
rb55877d rb5a3b50 38 38 #include <arch/mm.h> 39 39 40 /** Check if caching can be enabled for a given memory section. 41 * 42 * Memory areas used for I/O are excluded from caching. 43 * At the moment caching is enabled only on GTA02. 44 * 45 * @param section The section number. 46 * 47 * @return 1 if the given section can be mapped as cacheable, 0 otherwise. 48 */ 49 static inline int section_cacheable(pfn_t section) 50 { 51 #ifdef MACHINE_gta02 52 unsigned long address = section << PTE_SECTION_SHIFT; 53 54 if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END) 55 return 0; 56 else 57 return 1; 58 #else 59 return 0; 60 #endif 61 } 62 40 63 /** Initialize "section" page table entry. 41 64 * … … 55 78 pte->descriptor_type = PTE_DESCRIPTOR_SECTION; 56 79 pte->bufferable = 1; 57 pte->cacheable = 0;80 pte->cacheable = section_cacheable(frame); 58 81 pte->xn = 0; 59 82 pte->domain = 0; … … 123 146 "ldr r1, =0x00000005\n" 124 147 #else 148 #ifdef MACHINE_gta02 149 /* Mask to enable paging (bit 0), 150 D-cache (bit 2), I-cache (bit 12) */ 151 "ldr r1, =0x00001005\n" 152 #else 125 153 /* Mask to enable paging */ 126 154 "ldr r1, =0x00000001\n" 155 #endif 127 156 #endif 128 157 "orr r0, r0, r1\n"
Note:
See TracChangeset
for help on using the changeset viewer.