Changes in boot/arch/arm32/src/mm.c [ae86f89:b5a3b50] in mainline

File:

• boot/arch/arm32/src/mm.c (modified) (2 diffs)

boot/arch/arm32/src/mm.c

@@ -56 +56 @@
         else
                 return 1;
-#elif defined MACHINE_beagleboardxm
-        const unsigned long address = section << PTE_SECTION_SHIFT;
-        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
-                return 1;
+#else
+        return 0;
 #endif
-        return 0;
 }
 
@@ -133 +130 @@
                 "mcr p15, 0, r0, c3, c0, 0\n"
                 
-#ifdef PROCESSOR_ARCH_armv7_a
-                /* armv7 no longer requires cache entries to be invalid
-                 * upon reset, do this manually */
-                /* Invalidate ICache */
-                "mcr p15, 0, r0, c7, c5, 6\n"
-                //TODO: Invalidate data cache
+#ifdef PROCESSOR_armv7_a
+                /* Read Auxiliary control register */
+                "mrc p15, 0, r0, c1, c0, 1\n"
+                /* Mask to enable L2 cache */
+                "ldr r1, =0x00000002\n"
+                "orr r0, r0, r1\n"
+                /* Store Auxiliary control register */
+                "mrc p15, 0, r0, c1, c0, 1\n"
 #endif
-
                 /* Current settings */
                 "mrc p15, 0, r0, c1, c0, 0\n"
                 
-#if defined(PROCESSOR_cortex_a8) | defined(MACHINE_gta02)
-                /* Mask to enable paging, I-cache D-cache and branch predict
-                 * See kernel/arch/arm32/include/regutils.h for bit values.
-                 * It's safe because Cortex-A8 implements IVIPT extension
-                 * See Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245).
-                 * It's safe for gta02 too because we turn the caches off
-                 * before switching to kernel. */
-                "ldr r1, =0x00001805\n"
-#elif defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
-                /* Enable paging, data cache and branch prediction
-                 * see arch/arm32/src/cpu/cpu.c for reasoning */
-                "ldr r1, =0x00000805\n"
+#ifdef PROCESSOR_armv7_a
+                /* Mask to enable paging, caching */
+                "ldr r1, =0x00000005\n"
+#else
+#ifdef MACHINE_gta02
+                /* Mask to enable paging (bit 0),
+                   D-cache (bit 2), I-cache (bit 12) */
+                "ldr r1, =0x00001005\n"
 #else
                 /* Mask to enable paging */
                 "ldr r1, =0x00000001\n"
+#endif
 #endif
                 "orr r0, r0, r1\n"