Changes in boot/arch/arm32/src/mm.c [c6b601b:b5a3b50] in mainline

File:

• boot/arch/arm32/src/mm.c (modified) (3 diffs)

boot/arch/arm32/src/mm.c

@@ -38 +38 @@
 #include <arch/mm.h>
 
+/** Check if caching can be enabled for a given memory section.
+ *
+ * Memory areas used for I/O are excluded from caching.
+ * At the moment caching is enabled only on GTA02.
+ *
+ * @param section       The section number.
+ *
+ * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
+*/
+static inline int section_cacheable(pfn_t section)
+{
+#ifdef MACHINE_gta02
+        unsigned long address = section << PTE_SECTION_SHIFT;
+
+        if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
+                return 0;
+        else
+                return 1;
+#else
+        return 0;
+#endif
+}
+
 /** Initialize "section" page table entry.
  *
@@ -55 +78 @@
         pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
         pte->bufferable = 1;
-        pte->cacheable = 0;
+        pte->cacheable = section_cacheable(frame);
         pte->xn = 0;
         pte->domain = 0;
@@ -123 +146 @@
                 "ldr r1, =0x00000005\n"
 #else
+#ifdef MACHINE_gta02
+                /* Mask to enable paging (bit 0),
+                   D-cache (bit 2), I-cache (bit 12) */
+                "ldr r1, =0x00001005\n"
+#else
                 /* Mask to enable paging */
                 "ldr r1, =0x00000001\n"
+#endif
 #endif
                 "orr r0, r0, r1\n"