Changeset b5e0bb8 in mainline


Ignore:
Timestamp:
2006-02-01T23:06:10Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
4e147a6
Parents:
071a8ae6
Message:

sparc64 bugfix.
When disabling IMMU and DMMU the kernel has to perform synchronization operation
(e.g flush %r or membar #Sync instruction). There is no guarantee that the address
contained in %r is in DTLB and therefore the flush instruction can fault. Normally
this would be recognized and fixed by the OpenFirmware Fast Data MMU fault handler.
However, this handler lives in virtually mapped memory and an attempt to execute
there while the MMUs are disabled would result in a nested trap leading to error state.
Replacing flush %r instruction with membar #Sync, wich is sufficient in this case,
fixes this problem.

Location:
arch
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • arch/ia64/src/mm/frame.c

    r071a8ae6 rb5e0bb8  
    4545         */
    4646        frame_region_not_free(ROM_BASE, ROM_SIZE);
    47         zone_create_in_region(0, config.memory_size & ~(FRAME_SIZE-1));
     47       
     48        zone_create_in_region(0, config.memory_size & ~(FRAME_SIZE-1));
    4849}
  • arch/sparc64/include/barrier.h

    r071a8ae6 rb5e0bb8  
    5252}
    5353
     54static inline void membar(void)
     55{
     56        __asm__ volatile ("membar #Sync\n");
     57}
     58
    5459#endif
  • arch/sparc64/include/mm/mmu.h

    r071a8ae6 rb5e0bb8  
    111111        cr.im = enable;
    112112        asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
    113         flush();
     113        membar();
    114114}
    115115
     
    122122        cr.dm = enable;
    123123        asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
    124         flush();
     124        membar();
    125125}
    126126
  • arch/sparc64/include/mm/page.h

    r071a8ae6 rb5e0bb8  
    4242
    4343/** Implementation of page hash table interface. */
    44 #define HT_WIDTH_ARCH                   FRAME_WIDTH
     44#define HT_WIDTH_ARCH                   20      /* 1M */
    4545#define HT_HASH_ARCH(page, asid)        0
    4646#define HT_COMPARE_ARCH(page, asid, t)  0
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