Changes in kernel/arch/ppc32/src/asm.S [da52547:b60c582] in mainline
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kernel/arch/ppc32/src/asm.S
rda52547 rb60c582 1 /* 2 *Copyright (c) 2005 Martin Decky3 *All rights reserved.4 * 5 *Redistribution and use in source and binary forms, with or without6 *modification, are permitted provided that the following conditions7 *are met:8 * 9 *- Redistributions of source code must retain the above copyright10 *notice, this list of conditions and the following disclaimer.11 *- Redistributions in binary form must reproduce the above copyright12 *notice, this list of conditions and the following disclaimer in the13 *documentation and/or other materials provided with the distribution.14 *- The name of the author may not be used to endorse or promote products15 *derived from this software without specific prior written permission.16 * 17 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR18 *IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES19 *OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.20 *IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,21 *INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT22 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,23 *DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY24 *THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT25 *(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF26 *THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.27 */ 1 # 2 # Copyright (c) 2005 Martin Decky 3 # All rights reserved. 4 # 5 # Redistribution and use in source and binary forms, with or without 6 # modification, are permitted provided that the following conditions 7 # are met: 8 # 9 # - Redistributions of source code must retain the above copyright 10 # notice, this list of conditions and the following disclaimer. 11 # - Redistributions in binary form must reproduce the above copyright 12 # notice, this list of conditions and the following disclaimer in the 13 # documentation and/or other materials provided with the distribution. 14 # - The name of the author may not be used to endorse or promote products 15 # derived from this software without specific prior written permission. 16 # 17 # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 # 28 28 29 29 #include <arch/asm/regname.h> 30 #include <arch/cpu.h>31 30 32 31 .text … … 42 41 .global memcpy_from_uspace_failover_address 43 42 .global memcpy_to_uspace_failover_address 44 .global early_putchar45 43 46 44 userspace_asm: 47 48 /* 49 * r3 = uspace_uarg 50 * r4 = stack 51 * r5 = entry 52 */ 53 54 /* Disable interrupts */ 55 45 46 # r3 = uspace_uarg 47 # r4 = stack 48 # r5 = entry 49 50 # disable interrupts 51 56 52 mfmsr r31 57 53 rlwinm r31, r31, 0, 17, 15 58 54 mtmsr r31 59 55 60 /* Set entry point */56 # set entry point 61 57 62 58 mtsrr0 r5 63 59 64 /* Set problem state, enable interrupts */65 66 ori r31, r31, MSR_PR67 ori r31, r31, MSR_EE60 # set problem state, enable interrupts 61 62 ori r31, r31, msr_pr 63 ori r31, r31, msr_ee 68 64 mtsrr1 r31 69 65 70 /* Set stack */66 # set stack 71 67 72 68 mr sp, r4 73 74 /* %r6 is defined to hold pcb_ptr - set it to 0 */75 69 70 # %r6 is defined to hold pcb_ptr - set it to 0 71 76 72 xor r6, r6, r6 77 73 78 /* Jump to userspace */74 # jump to userspace 79 75 80 76 rfi … … 82 78 iret: 83 79 84 /* Disable interrupts */80 # disable interrupts 85 81 86 82 mfmsr r31 … … 144 140 iret_syscall: 145 141 146 /* Reset decrementer */147 142 # reset decrementer 143 148 144 li r31, 1000 149 145 mtdec r31 150 146 151 /* Disable interrupts */147 # disable interrupts 152 148 153 149 mfmsr r31 … … 205 201 lwz r12, 156(sp) 206 202 lwz sp, 160(sp) 207 203 208 204 rfi 209 205 … … 217 213 memcpy_from_uspace: 218 214 memcpy_to_uspace: 219 215 220 216 srwi. r7, r5, 3 221 217 addi r6, r3, -4 222 218 addi r4, r4, -4 223 beq 219 beq 2f 224 220 225 221 andi. r0, r6, 3 … … 229 225 1: 230 226 231 232 233 234 235 236 237 227 lwz r7, 4(r4) 228 lwzu r8, 8(r4) 229 stw r7, 4(r6) 230 stwu r8, 8(r6) 231 bdnz 1b 232 233 andi. r5, r5, 7 238 234 239 235 2: 240 236 241 242 243 244 245 246 237 cmplwi 0, r5, 4 238 blt 3f 239 240 lwzu r0, 4(r4) 241 addi r5, r5, -4 242 stwu r0, 4(r6) 247 243 248 244 3: 249 245 250 251 252 253 254 246 cmpwi 0, r5, 0 247 beqlr 248 mtctr r5 249 addi r4, r4, 3 250 addi r6, r6, 3 255 251 256 252 4: 257 253 258 259 260 261 254 lbzu r0, 1(r4) 255 stbu r0, 1(r6) 256 bdnz 4b 257 blr 262 258 263 259 5: 264 260 265 266 261 subfic r0, r0, 4 262 mtctr r0 267 263 268 264 6: 269 265 270 271 272 273 274 275 276 277 278 279 266 lbz r7, 4(r4) 267 addi r4, r4, 1 268 stb r7, 4(r6) 269 addi r6, r6, 1 270 bdnz 6b 271 subf r5, r0, r5 272 rlwinm. r7, r5, 32-3, 3, 31 273 beq 2b 274 mtctr r7 275 b 1b 280 276 281 277 memcpy_from_uspace_failover_address: 282 278 memcpy_to_uspace_failover_address: 283 /* Return zero, failure */279 # return zero, failure 284 280 xor r3, r3, r3 285 281 blr 286 287 early_putchar:288 blr
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