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  • kernel/arch/ppc32/src/asm.S

    rda52547 rb60c582  
    1 /*
    2  * Copyright (c) 2005 Martin Decky
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  *
    9  * - Redistributions of source code must retain the above copyright
    10  *   notice, this list of conditions and the following disclaimer.
    11  * - Redistributions in binary form must reproduce the above copyright
    12  *   notice, this list of conditions and the following disclaimer in the
    13  *   documentation and/or other materials provided with the distribution.
    14  * - The name of the author may not be used to endorse or promote products
    15  *   derived from this software without specific prior written permission.
    16  *
    17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
    18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
    19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
    20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
    21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
    22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
    26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    27  */
     1#
     2# Copyright (c) 2005 Martin Decky
     3# All rights reserved.
     4#
     5# Redistribution and use in source and binary forms, with or without
     6# modification, are permitted provided that the following conditions
     7# are met:
     8#
     9# - Redistributions of source code must retain the above copyright
     10#   notice, this list of conditions and the following disclaimer.
     11# - Redistributions in binary form must reproduce the above copyright
     12#   notice, this list of conditions and the following disclaimer in the
     13#   documentation and/or other materials provided with the distribution.
     14# - The name of the author may not be used to endorse or promote products
     15#   derived from this software without specific prior written permission.
     16#
     17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27#
    2828
    2929#include <arch/asm/regname.h>
    30 #include <arch/cpu.h>
    3130
    3231.text
     
    4241.global memcpy_from_uspace_failover_address
    4342.global memcpy_to_uspace_failover_address
    44 .global early_putchar
    4543
    4644userspace_asm:
    47        
    48         /*
    49          * r3 = uspace_uarg
    50          * r4 = stack
    51          * r5 = entry
    52          */
    53        
    54         /* Disable interrupts */
    55        
     45
     46        # r3 = uspace_uarg
     47        # r4 = stack
     48        # r5 = entry
     49       
     50        # disable interrupts
     51
    5652        mfmsr r31
    5753        rlwinm r31, r31, 0, 17, 15
    5854        mtmsr r31
    5955       
    60         /* Set entry point */
     56        # set entry point
    6157       
    6258        mtsrr0 r5
    6359       
    64         /* Set problem state, enable interrupts */
    65        
    66         ori r31, r31, MSR_PR
    67         ori r31, r31, MSR_EE
     60        # set problem state, enable interrupts
     61       
     62        ori r31, r31, msr_pr
     63        ori r31, r31, msr_ee
    6864        mtsrr1 r31
    6965       
    70         /* Set stack */
     66        # set stack
    7167       
    7268        mr sp, r4
    73        
    74         /* %r6 is defined to hold pcb_ptr - set it to 0 */
    75        
     69
     70        # %r6 is defined to hold pcb_ptr - set it to 0
     71
    7672        xor r6, r6, r6
    7773       
    78         /* Jump to userspace */
     74        # jump to userspace
    7975       
    8076        rfi
     
    8278iret:
    8379       
    84         /* Disable interrupts */
     80        # disable interrupts
    8581       
    8682        mfmsr r31
     
    144140iret_syscall:
    145141       
    146         /* Reset decrementer */
    147        
     142        # reset decrementer
     143
    148144        li r31, 1000
    149145        mtdec r31
    150146       
    151         /* Disable interrupts */
     147        # disable interrupts
    152148       
    153149        mfmsr r31
     
    205201        lwz r12, 156(sp)
    206202        lwz sp, 160(sp)
    207        
     203
    208204        rfi
    209205
     
    217213memcpy_from_uspace:
    218214memcpy_to_uspace:
    219        
     215
    220216        srwi. r7, r5, 3
    221217        addi r6, r3, -4
    222218        addi r4, r4, -4
    223         beq 2f
     219        beq     2f
    224220       
    225221        andi. r0, r6, 3
     
    229225        1:
    230226       
    231                 lwz r7, 4(r4)
    232                 lwzu r8, 8(r4)
    233                 stw r7, 4(r6)
    234                 stwu r8, 8(r6)
    235                 bdnz 1b
    236                
    237                 andi. r5, r5, 7
     227        lwz r7, 4(r4)
     228        lwzu r8, 8(r4)
     229        stw r7, 4(r6)
     230        stwu r8, 8(r6)
     231        bdnz 1b
     232       
     233        andi. r5, r5, 7
    238234       
    239235        2:
    240236       
    241                 cmplwi 0, r5, 4
    242                 blt 3f
    243                
    244                 lwzu r0, 4(r4)
    245                 addi r5, r5, -4
    246                 stwu r0, 4(r6)
     237        cmplwi 0, r5, 4
     238        blt 3f
     239       
     240        lwzu r0, 4(r4)
     241        addi r5, r5, -4
     242        stwu r0, 4(r6)
    247243       
    248244        3:
    249245       
    250                 cmpwi 0, r5, 0
    251                 beqlr
    252                 mtctr r5
    253                 addi r4, r4, 3
    254                 addi r6, r6, 3
     246        cmpwi 0, r5, 0
     247        beqlr
     248        mtctr r5
     249        addi r4, r4, 3
     250        addi r6, r6, 3
    255251       
    256252        4:
    257253       
    258                 lbzu r0, 1(r4)
    259                 stbu r0, 1(r6)
    260                 bdnz 4b
    261                 blr
     254        lbzu r0, 1(r4)
     255        stbu r0, 1(r6)
     256        bdnz 4b
     257        blr
    262258       
    263259        5:
    264260       
    265                 subfic r0, r0, 4
    266                 mtctr r0
     261        subfic r0, r0, 4
     262        mtctr r0
    267263       
    268264        6:
    269265       
    270                 lbz r7, 4(r4)
    271                 addi r4, r4, 1
    272                 stb r7, 4(r6)
    273                 addi r6, r6, 1
    274                 bdnz 6b
    275                 subf r5, r0, r5
    276                 rlwinm. r7, r5, 32-3, 3, 31
    277                 beq 2b
    278                 mtctr r7
    279                 b 1b
     266        lbz r7, 4(r4)
     267        addi r4, r4, 1
     268        stb r7, 4(r6)
     269        addi r6, r6, 1
     270        bdnz 6b
     271        subf r5, r0, r5
     272        rlwinm. r7, r5, 32-3, 3, 31
     273        beq 2b
     274        mtctr r7
     275        b 1b
    280276
    281277memcpy_from_uspace_failover_address:
    282278memcpy_to_uspace_failover_address:
    283         /* Return zero, failure */
     279        # return zero, failure
    284280        xor r3, r3, r3
    285281        blr
    286 
    287 early_putchar:
    288         blr
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