Changes in kernel/arch/ppc32/src/exception.S [9d58539:b66cc97] in mainline
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kernel/arch/ppc32/src/exception.S
r9d58539 rb66cc97 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/asm/regname.h> 30 31 #include <arch/msr.h> 31 32 #include <arch/mm/page.h> 33 #include <arch/istate_struct.h> 34 #include <arch/stack.h> 35 #include <align.h> 32 36 33 37 .section K_UNMAPPED_TEXT_START, "ax" … … 42 46 mtsprg2 sp 43 47 44 # check whether SP is in kernel 45 46 andis. sp, sp, 0x8000 48 # check whether the previous mode was user or kernel 49 50 mfsrr1 sp # use sp as a temporary register to hold SRR1 51 andi. sp, sp, MSR_PR 47 52 bne 1f 48 49 # stack is in user-space 50 51 mfsprg0 sp 52 53 b 2f 54 55 1: 56 57 # stack is in kernel 53 # previous mode was kernel 58 54 59 55 mfsprg2 sp 60 56 subis sp, sp, 0x8000 61 57 b 2f 58 59 1: 60 # previous mode was user 61 62 mfsprg0 sp 62 63 2: 63 64 64 subi sp, sp, 16465 stw r0, 8(sp)66 stw r2, 12(sp)67 stw r3, 16(sp)68 stw r4, 20(sp)69 stw r5, 24(sp)70 stw r6, 28(sp)71 stw r7, 32(sp)72 stw r8, 36(sp)73 stw r9, 40(sp)74 stw r10, 44(sp)75 stw r11, 48(sp)76 stw r13, 52(sp)77 stw r14, 56(sp)78 stw r15, 60(sp)79 stw r16, 64(sp)80 stw r17, 68(sp)81 stw r18, 72(sp)82 stw r19, 76(sp)83 stw r20, 80(sp)84 stw r21, 84(sp)85 stw r22, 88(sp)86 stw r23, 92(sp)87 stw r24, 96(sp)88 stw r25, 100(sp)89 stw r26, 104(sp)90 stw r27, 108(sp)91 stw r28, 112(sp)92 stw r29, 116(sp)93 stw r30, 120(sp)94 stw r31, 124(sp)95 96 stw r12, 128(sp)65 subi sp, sp, ALIGN_UP(ISTATE_SIZE, STACK_ALIGNMENT) 66 stw r0, ISTATE_OFFSET_R0(sp) 67 stw r2, ISTATE_OFFSET_R2(sp) 68 stw r3, ISTATE_OFFSET_R3(sp) 69 stw r4, ISTATE_OFFSET_R4(sp) 70 stw r5, ISTATE_OFFSET_R5(sp) 71 stw r6, ISTATE_OFFSET_R6(sp) 72 stw r7, ISTATE_OFFSET_R7(sp) 73 stw r8, ISTATE_OFFSET_R8(sp) 74 stw r9, ISTATE_OFFSET_R9(sp) 75 stw r10, ISTATE_OFFSET_R10(sp) 76 stw r11, ISTATE_OFFSET_R11(sp) 77 stw r13, ISTATE_OFFSET_R13(sp) 78 stw r14, ISTATE_OFFSET_R14(sp) 79 stw r15, ISTATE_OFFSET_R15(sp) 80 stw r16, ISTATE_OFFSET_R16(sp) 81 stw r17, ISTATE_OFFSET_R17(sp) 82 stw r18, ISTATE_OFFSET_R18(sp) 83 stw r19, ISTATE_OFFSET_R19(sp) 84 stw r20, ISTATE_OFFSET_R20(sp) 85 stw r21, ISTATE_OFFSET_R21(sp) 86 stw r22, ISTATE_OFFSET_R22(sp) 87 stw r23, ISTATE_OFFSET_R23(sp) 88 stw r24, ISTATE_OFFSET_R24(sp) 89 stw r25, ISTATE_OFFSET_R25(sp) 90 stw r26, ISTATE_OFFSET_R26(sp) 91 stw r27, ISTATE_OFFSET_R27(sp) 92 stw r28, ISTATE_OFFSET_R28(sp) 93 stw r29, ISTATE_OFFSET_R29(sp) 94 stw r30, ISTATE_OFFSET_R30(sp) 95 stw r31, ISTATE_OFFSET_R31(sp) 96 97 stw r12, ISTATE_OFFSET_CR(sp) 97 98 98 99 mfsrr0 r12 99 stw r12, 132(sp)100 stw r12, ISTATE_OFFSET_PC(sp) 100 101 101 102 mfsrr1 r12 102 stw r12, 136(sp)103 stw r12, ISTATE_OFFSET_SRR1(sp) 103 104 104 105 mflr r12 105 stw r12, 140(sp)106 stw r12, ISTATE_OFFSET_LR(sp) 106 107 107 108 mfctr r12 108 stw r12, 144(sp)109 stw r12, ISTATE_OFFSET_CTR(sp) 109 110 110 111 mfxer r12 111 stw r12, 148(sp)112 stw r12, ISTATE_OFFSET_XER(sp) 112 113 113 114 mfdar r12 114 stw r12, 152(sp)115 stw r12, ISTATE_OFFSET_DAR(sp) 115 116 116 117 mfsprg1 r12 117 stw r12, 156(sp)118 stw r12, ISTATE_OFFSET_R12(sp) 118 119 119 120 mfsprg2 r12 120 stw r12, 160(sp) 121 stw r12, ISTATE_OFFSET_SP(sp) 122 123 li r12, 0 124 stw r12, ISTATE_OFFSET_LR_FRAME(sp) 125 stw r12, ISTATE_OFFSET_SP_FRAME(sp) 121 126 .endm 122 127 123 128 .org 0x100 124 .global exc_system_reset 125 exc_system_reset: 129 SYMBOL(exc_system_reset) 126 130 CONTEXT_STORE 127 131 … … 130 134 131 135 .org 0x200 132 .global exc_machine_check 133 exc_machine_check: 136 SYMBOL(exc_machine_check) 134 137 CONTEXT_STORE 135 138 … … 138 141 139 142 .org 0x300 140 .global exc_data_storage 141 exc_data_storage: 143 SYMBOL(exc_data_storage) 142 144 CONTEXT_STORE 143 145 … … 146 148 147 149 .org 0x400 148 .global exc_instruction_storage 149 exc_instruction_storage: 150 SYMBOL(exc_instruction_storage) 150 151 CONTEXT_STORE 151 152 … … 154 155 155 156 .org 0x500 156 .global exc_external 157 exc_external: 157 SYMBOL(exc_external) 158 158 CONTEXT_STORE 159 159 … … 162 162 163 163 .org 0x600 164 .global exc_alignment 165 exc_alignment: 164 SYMBOL(exc_alignment) 166 165 CONTEXT_STORE 167 166 … … 170 169 171 170 .org 0x700 172 .global exc_program 173 exc_program: 171 SYMBOL(exc_program) 174 172 CONTEXT_STORE 175 173 … … 178 176 179 177 .org 0x800 180 .global exc_fp_unavailable 181 exc_fp_unavailable: 178 SYMBOL(exc_fp_unavailable) 182 179 CONTEXT_STORE 183 180 … … 186 183 187 184 .org 0x900 188 .global exc_decrementer 189 exc_decrementer: 185 SYMBOL(exc_decrementer) 190 186 CONTEXT_STORE 191 187 … … 194 190 195 191 .org 0xa00 196 .global exc_reserved0 197 exc_reserved0: 192 SYMBOL(exc_reserved0) 198 193 CONTEXT_STORE 199 194 … … 202 197 203 198 .org 0xb00 204 .global exc_reserved1 205 exc_reserved1: 199 SYMBOL(exc_reserved1) 206 200 CONTEXT_STORE 207 201 … … 210 204 211 205 .org 0xc00 212 .global exc_syscall 213 exc_syscall: 206 SYMBOL(exc_syscall) 214 207 CONTEXT_STORE 215 208 … … 217 210 218 211 .org 0xd00 219 .global exc_trace 220 exc_trace: 212 SYMBOL(exc_trace) 221 213 CONTEXT_STORE 222 214 … … 225 217 226 218 .org 0x1000 227 .global exc_itlb_miss 228 exc_itlb_miss: 219 SYMBOL(exc_itlb_miss) 229 220 CONTEXT_STORE 230 221 … … 233 224 234 225 .org 0x1100 235 .global exc_dtlb_miss_load 236 exc_dtlb_miss_load: 226 SYMBOL(exc_dtlb_miss_load) 237 227 CONTEXT_STORE 238 228 … … 241 231 242 232 .org 0x1200 243 .global exc_dtlb_miss_store 244 exc_dtlb_miss_store: 233 SYMBOL(exc_dtlb_miss_store) 245 234 CONTEXT_STORE 246 235 … … 250 239 .org 0x4000 251 240 jump_to_kernel: 241 mfsrr1 r5 242 andi. r5, r5, MSR_PR 243 bne 1f 244 # Previous mode was kernel. 245 # We can construct a proper frame linkage. 246 247 mfsrr0 r12 248 stw r12, ISTATE_OFFSET_LR_FRAME(sp) 249 mfsprg2 r12 250 stw r12, ISTATE_OFFSET_SP_FRAME(sp) 251 1: 252 252 253 lis r12, iret@ha 253 254 addi r12, r12, iret@l 254 255 mtlr r12 255 256 256 257 lis r12, exc_dispatch@ha 257 258 addi r12, r12, exc_dispatch@l 258 259 mtsrr0 r12 259 260 260 261 mfmsr r12 261 ori r12, r12, (MSR_IR | MSR_DR)@l 262 mfsrr1 r5 263 andi. r5, r5, MSR_FP 264 or r12, r12, r5 # Propagate MSR_FP from SRR1 to MSR 265 ori r12, r12, (MSR_IR | MSR_DR) 262 266 mtsrr1 r12 263 267 264 268 addis sp, sp, 0x8000 265 269 mr r4, sp 266 addi r4, r4, 8267 270 268 271 rfi … … 276 279 addi r12, r12, iret_syscall@l 277 280 mtlr r12 278 281 282 mfsrr1 r0 283 andi. r0, r0, MSR_FP 279 284 mfmsr r12 280 ori r12, r12, (MSR_IR | MSR_DR)@l 285 or r12, r12, r0 # Propagate MSR_FP from SRR1 to MSR 286 ori r12, r12, (MSR_IR | MSR_DR | MSR_EE) 281 287 mtsrr1 r12 282 288
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