Changeset b80d132 in mainline

Timestamp:

2013-01-23T20:48:23Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

df334ca

Parents:

bfb6576

Message:

arm32, boot: Flush everything to PoC (memory) and disable caches before reaching kernel

This should be safe for all ARMs. Kernel will enable caches if it is supported.

Location:

boot/arch/arm32/src

Files:

• asm.S (modified) (2 diffs)
• main.c (modified) (2 diffs)

boot/arch/arm32/src/asm.S

@@ -66 +66 @@
         # r2 is a kernel text end
 
+#define CP15_C1_IC              12
+#define CP15_C1_BP              11
+#define CP15_C1_DC              2
+        # Disable I-cache and D-cache before the kernel is started.
+        mrc     p15, 0, r4, c1, c0, 0
+        bic     r4, r4, #(1 << CP15_C1_DC)
+        bic     r4, r4, #(1 << CP15_C1_IC)
+        bic     r4, r4, #(1 << CP15_C1_BP)
+        mcr     p15, 0, r4, c1, c0, 0
+
         
         #Wait for the operations to complete
@@ -89 +99 @@
 #endif
         
+#TODO:This should not be necessary
 
 #if defined(MACHINE_gta02)
 
-#define CP15_C1_IC              12
-#define CP15_C1_DC              2
 #define CP15_C7_SEG_SHIFT       5
 #define CP15_C7_SEG_SIZE        3
 #define CP15_C7_IDX_SHIFT       26
-
-        # Disable I-cache and D-cache before the kernel is started.
-        mrc     p15, 0, r4, c1, c0, 0
-        bic     r4, r4, #(1 << CP15_C1_DC)
-        bic     r4, r4, #(1 << CP15_C1_IC)
-        mcr     p15, 0, r4, c1, c0, 0
 
         # Now clean D-cache to guarantee coherency between I-cache and D-cache.

boot/arch/arm32/src/main.c

@@ -69 +69 @@
 }
 
-static inline void clean_dcache_pou(void *address, size_t size)
+static inline void clean_dcache_poc(void *address, size_t size)
 {
         const uintptr_t addr = (uintptr_t)address;
-        /* DCCMVAU - clean by address to the point of unification */
+        /* DCCMVAC - clean by address to the point of coherence */
         for (uintptr_t a = addr; a < addr + size; a += 4) {
-                asm volatile ("mcr p15, 0, %[a], c7, c11, 1\n" :: [a]"r"(a) : );
+                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
         }
 }
@@ -148 +148 @@
                         halt();
                 }
-                clean_dcache_pou(dest[i - 1], components[i - 1].inflated);
+                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
         }