Changeset b9e97fb in mainline
- Timestamp:
- 2005-08-31T10:53:34Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8f91729
- Parents:
- 9756131
- Files:
-
- 2 added
- 19 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/Makefile.inc
r9756131 rb9e97fb 21 21 arch/context.S \ 22 22 arch/drivers/ega.c \ 23 arch/supplib.c 23 arch/drivers/i8042.c \ 24 arch/drivers/i8254.c \ 25 arch/drivers/i8259.c \ 26 arch/supplib.c \ 27 arch/delay.S \ 28 arch/amd64.c \ 29 arch/bios/bios.c 30 -
arch/amd64/include/asm.h
r9756131 rb9e97fb 35 35 36 36 void asm_delay_loop(__u32 t); 37 void asm_fake_loop(__u32 t); 38 37 39 38 40 /* TODO: implement the real stuff */ … … 55 57 :"=m"(out) 56 58 :"m"(port) 57 :" dx","al"59 :"%dx","%al" 58 60 ); 59 61 return out; … … 68 70 : 69 71 :"m"( port), "m" (b) 70 :" dx","al"72 :"%dx","%al" 71 73 ); 72 74 } … … 116 118 } 117 119 120 /** Return raw priority level 121 * 122 * Return EFLAFS. 123 */ 124 static inline pri_t cpu_priority_read(void) { 125 pri_t v; 126 __asm__ volatile ( 127 "pushfq\n" 128 "popq %0\n" 129 : "=r" (v) 130 ); 131 return v; 132 } 133 134 extern size_t interrupt_handler_size; 135 extern void interrupt_handlers(void); 118 136 119 137 #endif -
arch/amd64/include/interrupt.h
r9756131 rb9e97fb 1 1 /* 2 * Copyright (C) 200 5 Martin Decky2 * Copyright (C) 2001-2004 Jakub Jermar 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 #ifndef __ amd64_INTERRUPT_H__30 #define __ amd64_INTERRUPT_H__29 #ifndef __INTERRUPT_H__ 30 #define __INTERRUPT_H__ 31 31 32 extern void interrupt(void); 32 #include <arch/types.h> 33 #include <arch/pm.h> 34 35 #define IVT_ITEMS IDT_ITEMS 36 37 #define IVT_EXCBASE 0 38 #define EXCLAST 31 39 40 #define IVT_IRQBASE (IVT_EXCBASE+EXCLAST+1) 41 #define IRQLAST 15 42 43 #define IVT_FREEBASE (IVT_IRQBASE+IRQLAST+1) 44 45 #define IRQ_CLK 0 46 #define IRQ_KBD 1 47 #define IRQ_PIC1 2 48 #define IRQ_PIC_SPUR 7 49 50 /* this one must have four least significant bits set to ones */ 51 #define VECTOR_APIC_SPUR (IVT_ITEMS-1) 52 53 #if (((VECTOR_APIC_SPUR + 1)%16) || VECTOR_APIC_SPUR >= IVT_ITEMS) 54 #error Wrong definition of VECTOR_APIC_SPUR 55 #endif 56 57 #define VECTOR_PIC_SPUR (IVT_IRQBASE+IRQ_PIC_SPUR) 58 #define VECTOR_CLK (IVT_IRQBASE+IRQ_CLK) 59 #define VECTOR_KBD (IVT_IRQBASE+IRQ_KBD) 60 61 #define VECTOR_SYSCALL (IVT_FREEBASE+0) 62 #define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE+1) 63 #define VECTOR_WAKEUP_IPI (IVT_FREEBASE+2) 64 65 typedef void (* iroutine)(__u8 n, __native stack[]); 66 67 extern void (* disable_irqs_function)(__u16 irqmask); 68 extern void (* enable_irqs_function)(__u16 irqmask); 69 extern void (* eoi_function)(void); 70 71 extern iroutine trap_register(__u8 n, iroutine f); 72 73 extern void trap_dispatcher(__u8 n, __native stack[]); 74 75 extern void null_interrupt(__u8 n, __native stack[]); 76 extern void gp_fault(__u8 n, __native stack[]); 77 extern void nm_fault(__u8 n, __native stack[]); 78 extern void ss_fault(__u8 n, __native stack[]); 79 extern void page_fault(__u8 n, __native stack[]); 80 extern void syscall(__u8 n, __native stack[]); 81 extern void tlb_shootdown_ipi(__u8 n, __native stack[]); 82 extern void wakeup_ipi(__u8 n, __native stack[]); 83 84 extern void trap_virtual_enable_irqs(__u16 irqmask); 85 extern void trap_virtual_disable_irqs(__u16 irqmask); 86 extern void trap_virtual_eoi(void); 33 87 34 88 #endif -
arch/amd64/include/pm.h
r9756131 rb9e97fb 37 37 38 38 #define IDT_ITEMS 64 39 #define GDT_ITEMS 739 #define GDT_ITEMS 8 40 40 41 41 #define NULL_DES 0 … … 47 47 #define TSS_DES 6 48 48 49 #define selector(des) ((des)<<3) 49 #define gdtselector(des) ((des)<<3) 50 #define idtselector(des) ((des)<<4) 50 51 51 52 #define PL_KERNEL 0 … … 57 58 #define AR_WRITABLE (1<<1) 58 59 #define AR_READABLE (1<<1) 59 #define AR_INTERRUPT (0xe)60 60 #define AR_TSS (0x9) 61 #define AR_INTERRUPT (0xe) 62 #define AR_TRAP (0xf) 61 63 62 64 #define DPL_KERNEL (PL_KERNEL<<5) … … 66 68 67 69 #ifndef __ASM__ 68 69 struct ptr_16_32 {70 __u16 limit;71 __u32 base;72 } __attribute__ ((packed));73 70 74 71 struct descriptor { … … 85 82 } __attribute__ ((packed)); 86 83 84 struct tss_descriptor { 85 unsigned limit_0_15: 16; 86 unsigned base_0_15: 16; 87 unsigned base_16_23: 8; 88 unsigned type: 4; 89 unsigned reserve1 : 1; 90 unsigned dpl : 2; 91 unsigned present : 1; 92 unsigned limit_16_19: 4; 93 unsigned available: 1; 94 unsigned reserve2: 2; 95 unsigned granularity : 1; 96 unsigned base_24_31: 8; 97 unsigned base_32_63 : 32; 98 unsigned reserve3 : 32; 99 } __attribute__ ((packed)); 100 87 101 struct idescriptor { 88 102 unsigned offset_0_15: 16; 89 103 unsigned selector: 16; 90 unsigned unused: 8; 91 unsigned access: 8; 104 unsigned ist:3; 105 unsigned unused: 5; 106 unsigned type: 5; 107 unsigned dpl: 2; 108 unsigned present : 1; 92 109 unsigned offset_16_31: 16; 110 unsigned offset_32_63: 16; 111 unsigned reserved : 32; 93 112 } __attribute__ ((packed)); 94 113 114 struct ptr_16_64 { 115 __u16 limit; 116 __u64 base; 117 } __attribute__ ((packed)); 95 118 96 119 struct tss { 97 __u16 link; 98 unsigned : 16; 99 __u32 esp0; 100 __u16 ss0; 101 unsigned : 16; 102 __u32 esp1; 103 __u16 ss1; 104 unsigned : 16; 105 __u32 esp2; 106 __u16 ss2; 107 unsigned : 16; 108 __u32 cr3; 109 __u32 eip; 110 __u32 eflags; 111 __u32 eax; 112 __u32 ecx; 113 __u32 edx; 114 __u32 ebx; 115 __u32 esp; 116 __u32 ebp; 117 __u32 esi; 118 __u32 edi; 119 __u16 es; 120 unsigned : 16; 121 __u16 cs; 122 unsigned : 16; 123 __u16 ss; 124 unsigned : 16; 125 __u16 ds; 126 unsigned : 16; 127 __u16 fs; 128 unsigned : 16; 129 __u16 gs; 130 unsigned : 16; 131 __u16 ldtr; 132 unsigned : 16; 133 unsigned : 16; 134 __u16 io_map_base; 120 __u32 reserve1; 121 __u64 rsp0; 122 __u64 rsp1; 123 __u64 rsp2; 124 __u64 reserve2; 125 __u64 ist1; 126 __u64 ist2; 127 __u64 ist3; 128 __u64 ist4; 129 __u64 ist5; 130 __u64 ist6; 131 __u64 ist7; 132 __u64 reserve3; 133 __u16 reserve4; 134 __u16 iomap; 135 135 } __attribute__ ((packed)); 136 136 137 extern struct ptr_16_32 gdtr;138 137 extern struct tss *tss_p; 139 138 … … 141 140 extern struct idescriptor idt[]; 142 141 142 extern struct ptr_16_64 gdtr; 143 143 144 extern void pm_init(void); 144 145 145 extern void gdt_ setbase(struct descriptor *d, __address base);146 extern void gdt_ setlimit(struct descriptor *d, __u32 limit);146 extern void gdt_tss_setbase(struct descriptor *d, __address base); 147 extern void gdt_tss_setlimit(struct descriptor *d, __u32 limit); 147 148 148 149 extern void idt_init(void); -
arch/amd64/include/types.h
r9756131 rb9e97fb 37 37 typedef unsigned short __u16; 38 38 typedef unsigned int __u32; 39 typedef long long __u64;39 typedef unsigned long long __u64; 40 40 41 41 typedef __u64 __address; -
arch/amd64/src/boot/boot.S
r9756131 rb9e97fb 67 67 # Load gdtr, idtr 68 68 lgdt gdtr_inst 69 # Load idtr, but it contains mess - we should not get interrupt 70 # anyway 69 71 lidt idtr_inst 70 72 … … 73 75 movl %eax,%cr0 # switch to protected mode 74 76 75 jmpl $ selector(KTEXT32_DES), $now_in_prot77 jmpl $gdtselector(KTEXT32_DES), $now_in_prot 76 78 77 79 no_long_mode: … … 83 85 now_in_prot: 84 86 # Set up stack & data descriptors 85 movw $ selector(KDATA_DES), %ax87 movw $gdtselector(KDATA_DES), %ax 86 88 movw %ax, %ds 87 89 movw %ax, %fs … … 111 113 112 114 # At this point we are in compatibility mode 113 jmpl $ selector(KTEXT_DES), $start64115 jmpl $gdtselector(KTEXT_DES), $start64 114 116 115 117 .code64 … … 117 119 movq START_STACK_64, %rsp 118 120 119 lidt idtr_inst120 121 121 call main_bsp # never returns 122 122 1: 123 123 jmp 1b 124 125 124 126 125 .section K_DATA_START 127 126 .align 4096 127 128 # Identical mapping of first 16MB and the same of -2GB -> 0 128 129 .global ptl_2 129 130 ptl_2: … … 154 155 .global gdtr_inst 155 156 gdtr_inst: 156 .word selector(GDT_ITEMS)157 .word gdtselector(GDT_ITEMS) 157 158 .long KA2PA(gdt) 158 159 159 160 .global idtr_inst 160 161 idtr_inst: 161 .word 0162 .word idtselector(IDT_ITEMS) 162 163 .long KA2PA(idt) -
arch/amd64/src/dummy.s
r9756131 rb9e97fb 29 29 .text 30 30 31 .global cpu_priority_high32 .global cpu_priority_low33 .global cpu_priority_read34 .global cpu_priority_restore35 31 .global userspace 36 32 .global before_thread_runs_arch … … 41 37 .global cpu_print_report 42 38 .global get_memory_size 43 .global arch_pre_mm_init44 .global arch_post_mm_init45 39 .global arch_late_init 46 40 .global calibrate_delay_loop 47 .global asm_delay_loop48 41 .global cpu_halt 49 42 .global page_arch_init 50 43 .global frame_arch_init 51 44 .global dummy 52 .global asm_delay_loop 45 .global trap_register 46 .global trap_virtual_eoi 47 .global trap_virtual_enable_irqs 48 .global rdtsc 49 .global trap_virtual_disable_irqs 50 .global enable_irqs_function 51 .global disable_irqs_function 52 .global eoi_function 53 .global syscall 54 55 .global null_interrupt 56 .global interrupt_handler_size 57 .global gp_fault 58 .global nm_fault 59 .global ss_fault 60 .global tss_p 61 .global interrupt_handlers 53 62 .global memcpy 54 63 55 cpu_priority_high: 56 cpu_priority_low: 57 cpu_priority_restore: 58 cpu_priority_read: 59 asm_delay_loop: 64 null_interrupt: 65 interrupt_handler_size: 66 interrupt_handlers: 67 gp_fault: 68 nm_fault: 69 ss_fault: 70 tss_p: 71 72 eoi_function: 73 syscall: 74 enable_irqs_function: 75 disable_irqs_function: 76 rdtsc: 77 trap_virtual_eoi: 78 trap_virtual_enable_irqs: 79 trap_virtual_disable_irqs: 80 trap_register: 60 81 before_thread_runs_arch: 61 82 userspace: 62 83 calibrate_delay_loop: 63 asm_delay_loop:64 84 panic_printf: 65 85 cpu_identify: … … 68 88 cpu_print_report: 69 89 get_memory_size: 70 arch_pre_mm_init:71 arch_post_mm_init:72 90 arch_late_init: 73 91 calibrate_delay_loop: -
arch/amd64/src/pm.c
r9756131 rb9e97fb 30 30 #include <arch/mm/page.h> 31 31 #include <arch/types.h> 32 32 #include <arch/interrupt.h> 33 #include <arch/asm.h> 34 35 #include <config.h> 36 37 #include <memstr.h> 38 #include <mm/heap.h> 39 #include <debug.h> 33 40 34 41 /* … … 72 79 .longmode = 1, 73 80 .special = 0, 74 .granularity = 0,81 .granularity = 1, 75 82 .base_24_31 = 0 }, 76 83 /* UDATA descriptor */ … … 96 103 .granularity = 1, 97 104 .base_24_31 = 0 }, 98 /* TSS descriptor - set up will be completed later */ 105 /* TSS descriptor - set up will be completed later, 106 * on AMD64 it is 64-bit - 2 items in table */ 107 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 99 108 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 100 109 }; 101 110 111 struct ptr_16_64 gdtr = {.limit = sizeof(gdtr), .base= (__u64) &gdtr }; 112 102 113 struct idescriptor idt[IDT_ITEMS]; 103 114 104 115 static struct tss tss; 105 116 106 /* Does not compile correctly if it does not exist*/117 /* TODO: Does not compile correctly if it does not exist ???? */ 107 118 int __attribute__ ((section ("K_DATA_START"))) __fake; 119 120 void gdt_tss_setbase(struct descriptor *d, __address base) 121 { 122 struct tss_descriptor *td = (struct tss_descriptor *) d; 123 124 td->base_0_15 = base & 0xffff; 125 td->base_16_23 = ((base) >> 16) & 0xff; 126 td->base_24_31 = ((base) >> 24) & 0xff; 127 td->base_32_63 = ((base) >> 32); 128 } 129 130 void gdt_tss_setlimit(struct descriptor *d, __u32 limit) 131 { 132 struct tss_descriptor *td = (struct tss_descriptor *) d; 133 134 td->limit_0_15 = limit & 0xffff; 135 td->limit_16_19 = (limit >> 16) & 0xf; 136 } 137 138 void idt_setoffset(struct idescriptor *d, __address offset) 139 { 140 /* 141 * Offset is a linear address. 142 */ 143 d->offset_0_15 = offset & 0xffff; 144 d->offset_16_31 = offset >> 16 & 0xffff; 145 d->offset_32_63 = offset >> 32; 146 } 147 148 void tss_initialize(struct tss *t) 149 { 150 memsetb((__address) t, sizeof(struct tss), 0); 151 } 152 153 /* 154 * This function takes care of proper setup of IDT and IDTR. 155 */ 156 void idt_init(void) 157 { 158 struct idescriptor *d; 159 int i; 160 161 for (i = 0; i < IDT_ITEMS; i++) { 162 d = &idt[i]; 163 164 d->unused = 0; 165 d->selector = idtselector(KTEXT_DES); 166 167 d->present = 1; 168 d->type = AR_INTERRUPT; /* masking interrupt */ 169 170 if (i == VECTOR_SYSCALL) { 171 /* 172 * The syscall interrupt gate must be calleable from userland. 173 */ 174 d->dpl |= PL_USER; 175 } 176 177 idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); 178 trap_register(i, null_interrupt); 179 } 180 trap_register(13, gp_fault); 181 trap_register( 7, nm_fault); 182 trap_register(12, ss_fault); 183 } 184 185 186 /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ 187 static void clean_IOPL_NT_flags(void) 188 { 189 asm 190 ( 191 "pushfq;" 192 "pop %%rax;" 193 "and $~(0x7000),%%rax;" 194 "pushq %%rax;" 195 "popfq;" 196 : 197 : 198 :"%rax" 199 ); 200 } 201 202 /* Clean AM(18) flag in CR0 register */ 203 static void clean_AM_flag(void) 204 { 205 asm 206 ( 207 "mov %%cr0,%%rax;" 208 "and $~(0x40000),%%rax;" 209 "mov %%rax,%%cr0;" 210 : 211 : 212 :"%rax" 213 ); 214 } 215 216 void pm_init(void) 217 { 218 struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base); 219 struct tss_descriptor *tss_d; 220 221 /* 222 * Each CPU has its private GDT and TSS. 223 * All CPUs share one IDT. 224 */ 225 226 if (config.cpu_active == 1) { 227 idt_init(); 228 /* 229 * NOTE: bootstrap CPU has statically allocated TSS, because 230 * the heap hasn't been initialized so far. 231 */ 232 tss_p = &tss; 233 } 234 else { 235 tss_p = (struct tss *) malloc(sizeof(struct tss)); 236 if (!tss_p) 237 panic("could not allocate TSS\n"); 238 } 239 240 tss_initialize(tss_p); 241 242 tss_d = (struct tss_descriptor *) &gdt_p[TSS_DES]; 243 tss_d[TSS_DES].present = 1; 244 tss_d[TSS_DES].type = AR_TSS; 245 tss_d[TSS_DES].dpl = PL_KERNEL; 246 247 gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p); 248 gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1); 249 250 /* 251 * As of this moment, the current CPU has its own GDT pointing 252 * to its own TSS. We just need to load the TR register. 253 */ 254 __asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES))); 255 256 clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ 257 clean_AM_flag(); /* Disable alignment check */ 258 } -
arch/ia32/include/i8042.h
r9756131 rb9e97fb 33 33 34 34 extern void i8042_init(void); 35 extern void i8042_interrupt(__u8 n, __ u32stack[]);35 extern void i8042_interrupt(__u8 n, __native stack[]); 36 36 37 37 #endif -
arch/ia32/include/i8254.h
r9756131 rb9e97fb 33 33 34 34 extern void i8254_init(void); 35 extern void i8254_interrupt(__u8 n, __ u32stack[]);35 extern void i8254_interrupt(__u8 n, __native stack[]); 36 36 extern void i8254_calibrate_delay_loop(void); 37 37 extern void i8254_normal_operation(void); -
arch/ia32/include/i8259.h
r9756131 rb9e97fb 47 47 extern void pic_disable_irqs(__u16 irqmask); 48 48 extern void pic_eoi(void); 49 extern void pic_spurious(__u8 n, __ u32stack[]);49 extern void pic_spurious(__u8 n, __native stack[]); 50 50 51 51 #endif -
arch/ia32/include/interrupt.h
r9756131 rb9e97fb 63 63 #define VECTOR_WAKEUP_IPI (IVT_FREEBASE+2) 64 64 65 typedef void (* iroutine)(__u8 n, __u32 stack[]); 66 67 extern iroutine ivt[IVT_ITEMS]; 65 typedef void (* iroutine)(__u8 n, __native stack[]); 68 66 69 67 extern void (* disable_irqs_function)(__u16 irqmask); … … 73 71 extern iroutine trap_register(__u8 n, iroutine f); 74 72 75 extern void trap_dispatcher(__u8 n, __ u32stack[]);73 extern void trap_dispatcher(__u8 n, __native stack[]); 76 74 77 extern void null_interrupt(__u8 n, __ u32stack[]);78 extern void gp_fault(__u8 n, __ u32stack[]);79 extern void nm_fault(__u8 n, __ u32stack[]);80 extern void ss_fault(__u8 n, __ u32stack[]);81 extern void page_fault(__u8 n, __ u32stack[]);82 extern void syscall(__u8 n, __ u32stack[]);83 extern void tlb_shootdown_ipi(__u8 n, __ u32stack[]);84 extern void wakeup_ipi(__u8 n, __ u32stack[]);75 extern void null_interrupt(__u8 n, __native stack[]); 76 extern void gp_fault(__u8 n, __native stack[]); 77 extern void nm_fault(__u8 n, __native stack[]); 78 extern void ss_fault(__u8 n, __native stack[]); 79 extern void page_fault(__u8 n, __native stack[]); 80 extern void syscall(__u8 n, __native stack[]); 81 extern void tlb_shootdown_ipi(__u8 n, __native stack[]); 82 extern void wakeup_ipi(__u8 n, __native stack[]); 85 83 86 84 extern void trap_virtual_enable_irqs(__u16 irqmask); -
arch/ia32/include/pm.h
r9756131 rb9e97fb 133 133 134 134 extern struct descriptor gdt[]; 135 extern struct idescriptor idt[];136 135 137 136 extern void pm_init(void); -
arch/ia32/src/acpi/acpi.c
r9756131 rb9e97fb 42 42 43 43 struct acpi_signature_map signature_map[] = { 44 { "APIC", (struct acpi_sdt_header **) &acpi_madt, "Multiple APIC Description Table" }44 { (__u8 *)"APIC", (struct acpi_sdt_header **) &acpi_madt, "Multiple APIC Description Table" } 45 45 }; 46 46 -
arch/ia32/src/drivers/i8042.c
r9756131 rb9e97fb 49 49 } 50 50 51 void i8042_interrupt(__u8 n, __ u32stack[])51 void i8042_interrupt(__u8 n, __native stack[]) 52 52 { 53 53 __u8 x; -
arch/ia32/src/drivers/i8254.c
r9756131 rb9e97fb 123 123 } 124 124 125 void i8254_interrupt(__u8 n, __ u32stack[])125 void i8254_interrupt(__u8 n, __native stack[]) 126 126 { 127 127 trap_virtual_eoi(); -
arch/ia32/src/drivers/i8259.c
r9756131 rb9e97fb 116 116 } 117 117 118 void pic_spurious(__u8 n, __ u32stack[])118 void pic_spurious(__u8 n, __native stack[]) 119 119 { 120 120 printf("cpu%d: PIC spurious interrupt\n", CPU->id); -
src/build.amd64
r9756131 rb9e97fb 5 5 (cd ../arch/amd64/src;make gencontext;./gencontext) 6 6 # Create links to ia32 architecture 7 ln -sf ../../../arch/ia32/src/drivers ../arch/amd64/src/ 8 ln -sf ../../../arch/ia32/include/ega.h ../arch/amd64/include/ 7 for a in drivers bios; do 8 ln -sf ../../../arch/ia32/src/$a ../arch/amd64/src/ 9 done 9 10 11 for a in ega.h i8042.h i8259.h i8254.h cpuid.h interrupt.h bios; do 12 ln -sf ../../../arch/ia32/include/$a ../arch/amd64/include/ 13 done 14 15 make dist-clean ARCH=ia32 10 16 make all ARCH=amd64 -
src/clean.amd64
r9756131 rb9e97fb 2 2 3 3 make dist-clean ARCH=amd64 4 make dist-clean ARCH=ia32 5 6 find ../arch/amd64 -type l | xargs rm 7 rm ../arch/amd64/src/context_offset.h
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