Changeset bbb0a400 in mainline

Timestamp:

2012-09-04T20:49:53Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

d126d3e

Parents:

2ddb3c5

Message:

arm32: Optimize instruction recognition.

File:

• kernel/arch/arm32/src/mm/page_fault.c (modified) (1 diff)

kernel/arch/arm32/src/mm/page_fault.c

@@ -154 +154 @@
         } ls_inst[] = {
                 /* Store word */
-                { 0x0e700000, 0x04000000, PF_ACCESS_WRITE }, /*STR imm x2*/
-                { 0x0e700000, 0x04200000, PF_ACCESS_WRITE }, /*STR imm STRT*/
-                { 0x0e700010, 0x06000000, PF_ACCESS_WRITE }, /*STR reg x2*/
-                { 0x0e700010, 0x06200000, PF_ACCESS_WRITE }, /*STR reg STRT*/
+                { 0x0e500000, 0x04000000, PF_ACCESS_WRITE }, /*STR imm*/
+                { 0x0e500010, 0x06000000, PF_ACCESS_WRITE }, /*STR reg*/
                 /* Store byte */
-                { 0x0e700000, 0x04400000, PF_ACCESS_WRITE }, /*STRB imm x2*/
-                { 0x0e700000, 0x04600000, PF_ACCESS_WRITE }, /*STRB imm STRBT*/
-                { 0x0e700010, 0x06400000, PF_ACCESS_WRITE }, /*STRB reg x2*/
-                { 0x0e700010, 0x06600000, PF_ACCESS_WRITE }, /*STRB reg STRBT*/
+                { 0x0e500000, 0x04400000, PF_ACCESS_WRITE }, /*STRB imm*/
+                { 0x0e500010, 0x06400000, PF_ACCESS_WRITE }, /*STRB reg*/
                 /* Load word */
-                { 0x0e700000, 0x04100000, PF_ACCESS_READ }, /*LDR imm x2*/
-                { 0x0e700000, 0x04300000, PF_ACCESS_READ }, /*LDR imm LDRT*/
-                { 0x0e700010, 0x06100000, PF_ACCESS_READ }, /*LDR reg x2*/
-                { 0x0e700010, 0x06300000, PF_ACCESS_READ }, /*LDR reg LDRT*/
+                { 0x0e500000, 0x04100000, PF_ACCESS_READ }, /*LDR imm*/
+                { 0x0e500010, 0x06100000, PF_ACCESS_READ }, /*LDR reg*/
                 /* Load byte */
-                { 0x0e700000, 0x04500000, PF_ACCESS_READ }, /*LDRB imm x2*/
-                { 0x0e700000, 0x04700000, PF_ACCESS_READ }, /*LDRB imm LDRBT*/
-                { 0x0e700010, 0x06500000, PF_ACCESS_READ }, /*LDRB reg x2*/
-                { 0x0e700010, 0x06700000, PF_ACCESS_READ }, /*LDRB reg LDRBT*/
+                { 0x0e500000, 0x04500000, PF_ACCESS_READ }, /*LDRB imm x2*/
+                { 0x0e500010, 0x06500000, PF_ACCESS_READ }, /*LDRB reg x2*/
                 /* Store half-word/dual  A5.2.8 */
-                { 0x0e1000f0, 0x000000b0, PF_ACCESS_WRITE }, /*STRH imm reg*/
-                { 0x0e1000f0, 0x000000f0, PF_ACCESS_WRITE }, /*STRD imm reg*/
+                { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /*STRH imm reg*/
                 /* Load half-word/dual A5.2.8 */
-                { 0x0e1000f0, 0x001000b0, PF_ACCESS_READ }, /*LDRH imm reg*/
                 { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /*LDRH imm reg*/
-                { 0x0e1000f0, 0x001000f0, PF_ACCESS_READ }, /*LDRD imm reg*/
+                { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /*LDRH imm reg*/
                 /* Block data transfer, Store */
                 { 0x0e100000, 0x08000000, PF_ACCESS_WRITE }, /* STM variants */