Changeset bdc5c516 in mainline

Timestamp:

2006-05-03T08:18:01Z (19 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

22cf454d

Parents:

cc35e88

Message:

Added commands for accessing ia32 portspace in irq top-half.

Location:

generic

Files:

• include/ipc/irq.h (modified) (1 diff)
• src/ipc/irq.c (modified) (6 diffs)

generic/include/ipc/irq.h

@@ -41 +41 @@
         CMD_MEM_WRITE_4,
         CMD_MEM_WRITE_8,
+        CMD_PORT_READ_1,
+        CMD_PORT_WRITE_1,
         CMD_LAST
 } irq_cmd_type;

generic/src/ipc/irq.c

@@ -27 +27 @@
  */
 
+/** IRQ notification framework
+ *
+ * This framework allows applications to register to receive a notification
+ * when interrupt is detected. The application may provide a simple 'top-half'
+ * handler as part of its registration, which can perform simple operations
+ * (read/write port/memory, add information to notification ipc message).
+ *
+ * The structure of a notification message is as follows:
+ * - METHOD: IPC_M_INTERRUPT
+ * - ARG1: interrupt number
+ * - ARG2: payload modified by a 'top-half' handler
+ * - ARG3: interrupt counter (may be needed to assure correct order
+ *         in multithreaded drivers)
+ */
+
 #include <arch.h>
 #include <mm/slab.h>
@@ -32 +47 @@
 #include <ipc/ipc.h>
 #include <ipc/irq.h>
+#include <atomic.h>
 
 typedef struct {
@@ -37 +53 @@
         answerbox_t *box;
         irq_code_t *code;
+        atomic_t counter;
 } ipc_irq_t;
 
@@ -78 +95 @@
                         *((__u64 *)code->cmds[i].addr) = code->cmds[i].value;
                         break;
+#if defined(ia32) || defined(amd64)
+                case CMD_PORT_READ_1:
+                        IPC_SET_ARG2(call->data, inb((long)code->cmds[i].addr));
+                        break;
+                case CMD_PORT_WRITE_1:
+                        outb((long)code->cmds[i].addr, code->cmds[i].value);
+                        break;
+#endif
                 default:
                         break;
@@ -154 +179 @@
         irq_conns[irq].box = box;
         irq_conns[irq].code = code;
+        atomic_set(&irq_conns[irq].counter, 0);
         spinlock_unlock(&irq_conns[irq].lock);
         interrupts_restore(ipl);
@@ -176 +202 @@
                 IPC_SET_METHOD(call->data, IPC_M_INTERRUPT);
                 IPC_SET_ARG1(call->data, irq);
+                IPC_SET_ARG3(call->data, atomic_preinc(&irq_conns[irq].counter));
 
                 /* Execute code to handle irq */