Changeset bf2a269 in mainline

Timestamp:

2012-11-20T14:32:33Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

fde2dab9

Parents:

bf6f6ca

Message:

rootamdm37x: Setup DPLL5 during initialization.

Location:

uspace/drv/infrastructure/rootamdm37x

Files:

• cm/clock_control.h (modified) (2 diffs)
• rootamdm37x.c (modified) (1 diff)

uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h

@@ -67 +67 @@
 
         ioport32_t clken2_pll;
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG   (1 << 10)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG   (1 << 3)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_MASK   (0x7)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LP_STOP   (0x1)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LOCK   (0x7)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG   (1 << 10)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG   (1 << 3)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK   (0x7)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LP_STOP   (0x1)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK   (0x7)
 
         PADD32[6];
@@ -143 +143 @@
         ioport32_t clksel4_pll;
 #define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK   (0x7ff << 8)
-#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT(x)   (((x) & 0x7ff) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(x)   (((x) & 0x7ff) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_GET(x)   (((x) >> 8) & 0x7ff)
 #define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK   (0x7f)
-#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV(x)   ((x) & 0x7f)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(x)   ((x) & 0x7f)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_GET(x)   ((x) & 0x7f)
 
         ioport32_t clksel5_pll;
 #define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK   (0x1f)
-#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M(x)   ((x) & 0x1f)
+#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(x)   ((x) & 0x1f)
+#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_GET(x)   ((x) & 0x1f)
 } clock_control_cm_regs_t;
 

uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c

@@ -285 +285 @@
          */
         // TODO setup DPLL5
+        if ((pio_read_32(&device->cm.clocks->clken2_pll)
+                & CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK)
+            != CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) {
+                /* Compute divisors and multiplier */
+                assert((base_freq % 100) == 0);
+                const unsigned mult = 1200;
+                const unsigned div = base_freq / 100;
+                const unsigned div2 = 1;
+
+                /* Set multiplier */
+                pio_change_32(&device->cm.clocks->clksel4_pll,
+                    CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult),
+                    CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10);
+
+                /* Set DPLL divisor */
+                pio_change_32(&device->cm.clocks->clksel4_pll,
+                    CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div),
+                    CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10);
+
+                /* Set output clock divisor */
+                pio_change_32(&device->cm.clocks->clksel5_pll,
+                    CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2),
+                    CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10);
+
+                /* Start DPLL5 */
+                pio_change_32(&device->cm.clocks->clken2_pll,
+                    CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK,
+                    CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10);
+
+        }
         /* Set DPLL5 to automatic to save power */
         pio_change_32(&device->cm.clocks->autoidle2_pll,