Changeset bfb6576 in mainline

Timestamp:

2013-01-23T00:12:15Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b80d132

Parents:

c19808fd

Message:

arm32, boot: Rework boot time cache handling. Enable Icache early.

Dcache still hangs after jumping to kernel.

Location:

boot/arch/arm32

Files:

• _link.ld.in (modified) (2 diffs)
• src/asm.S (modified) (2 diffs)
• src/main.c (modified) (5 diffs)
• src/mm.c (modified) (3 diffs)

boot/arch/arm32/_link.ld.in

@@ -11 +11 @@
         . = BOOT_BASE + 0x8000;
         .data : {
+                bdata_start = .;
                 *(BOOTPT);      /* bootstrap page table */
                 *(BOOTSTACK);   /* bootstrap stack */
@@ -24 +25 @@
 [[COMPONENTS]]
         }
-        
+        bdata_end = .;
+
         /DISCARD/ : {
                 *(.gnu.*);

boot/arch/arm32/src/asm.S

@@ -66 +66 @@
         # r2 is a kernel text end
 
-        # make sure kernel is flushed and available in memory
-        # Disable I-cache and D-cache before the kernel is started.
-        # TODO disabling DCache should not be necessary...
-#define CP15_C1_IC              12
-#define CP15_C1_DC              2
-        mrc     p15, 0, r4, c1, c0, 0
-        bic     r4, r4, #(1 << CP15_C1_DC)
-        bic     r4, r4, #(1 << CP15_C1_IC)
-        mcr     p15, 0, r4, c1, c0, 0
-
-        # use r4 as a moving pointer
-        mov r4, r0
-3:
-        # DCCMVAC (flush by virt address, to the point of coherence)
-        mcr p15, 0, r4, c7, c10, 1
-        # TODO: it would be better to use cacheline size
-        add r4, r4, #4
-        # are we there yet?
-        cmp r4, r2
-        blt 3b
-        nop
-        mov r4, #0
         
         #Wait for the operations to complete
@@ -99 +77 @@
         # Clean ICache and BPredictors, r4 ignored (SBZ)
         mcr p15, 0, r4, c7, c5, 0
+        nop
 
         #Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
         isb
+        nop
 #else
         # cp15 isb
         mcr p15, 0, r4, c7, c5, 4
+        nop
 #endif
         

boot/arch/arm32/src/main.c

@@ -50 +50 @@
 #define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
 
+extern void *bdata_start;
+extern void *bdata_end;
+
+
+static inline void invalidate_icache(void)
+{
+        /* ICIALLU Invalidate entire ICache */
+        asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
+}
+
+static inline void invalidate_dcache(void *address, size_t size)
+{
+        const uintptr_t addr = (uintptr_t)address;
+        /* DCIMVAC - invalidate by address to the point of coherence */
+        for (uintptr_t a = addr; a < addr + size; a += 4) {
+                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
+        }
+}
+
+static inline void clean_dcache_pou(void *address, size_t size)
+{
+        const uintptr_t addr = (uintptr_t)address;
+        /* DCCMVAU - clean by address to the point of unification */
+        for (uintptr_t a = addr; a < addr + size; a += 4) {
+                asm volatile ("mcr p15, 0, %[a], c7, c11, 1\n" :: [a]"r"(a) : );
+        }
+}
+
 static bootinfo_t bootinfo;
 
 void bootstrap(void)
 {
+        /* Make sure  we run in memory code when caches are enabled,
+         * make sure we read memory data too. This part is ARMv7 specific as
+         * ARMv7 no longer invalidates caches on restart.
+         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
+        invalidate_icache();
+        invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
+
+        /* Enable MMU and caches */
         mmu_start();
         version_print();
         
+        printf("Boot data: %p -> %p\n", &bdata_start, &bdata_end);
         printf("\nMemory statistics\n");
         printf(" %p|%p: bootstrap stack\n", &boot_stack, &boot_stack);
@@ -64 +101 @@
             (void *) PA2KA(BOOT_OFFSET), (void *) BOOT_OFFSET);
         
-        size_t i;
-        for (i = 0; i < COMPONENTS; i++)
+        for (size_t i = 0; i < COMPONENTS; i++) {
                 printf(" %p|%p: %s image (%u/%u bytes)\n", components[i].start,
                     components[i].start, components[i].name, components[i].inflated,
                     components[i].size);
+                invalidate_dcache(components[i].start, components[i].size);
+        }
         
         void *dest[COMPONENTS];
@@ -74 +112 @@
         size_t cnt = 0;
         bootinfo.cnt = 0;
-        for (i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
+        for (size_t i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
                 top = ALIGN_UP(top, PAGE_SIZE);
                 
@@ -94 +132 @@
         printf("\nInflating components ... ");
         
-        for (i = cnt; i > 0; i--) {
+        for (size_t i = cnt; i > 0; i--) {
                 void *tail = components[i - 1].start + components[i - 1].size;
                 if (tail >= dest[i - 1]) {
@@ -106 +144 @@
                 int err = inflate(components[i - 1].start, components[i - 1].size,
                     dest[i - 1], components[i - 1].inflated);
-                
                 if (err != EOK) {
                         printf("\n%s: Inflating error %d\n", components[i - 1].name, err);
                         halt();
                 }
+                clean_dcache_pou(dest[i - 1], components[i - 1].inflated);
         }
         

boot/arch/arm32/src/mm.c

@@ -59 +59 @@
         const unsigned long address = section << PTE_SECTION_SHIFT;
         if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
-                return 0;
+                return 1;
 #endif
         return 0;
@@ -133 +133 @@
                 "mcr p15, 0, r0, c3, c0, 0\n"
                 
-#ifdef PROCESSOR_ARCH_armv7_a
-                /* armv7 no longer requires cache entries to be invalid
-                 * upon reset, do this manually */
-                /* Invalidate ICache */
-                "mcr p15, 0, r0, c7, c5, 6\n"
-                //TODO: Invalidate data cache
-#endif
-
                 /* Current settings */
                 "mrc p15, 0, r0, c1, c0, 0\n"
@@ -151 +143 @@
                  * It's safe for gta02 too because we turn the caches off
                  * before switching to kernel. */
-                "ldr r1, =0x00001805\n"
+                "ldr r1, =0x00001801\n"
 #elif defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
                 /* Enable paging, data cache and branch prediction