Changeset c03ee1c in mainline


Ignore:
Timestamp:
2007-06-13T17:49:57Z (18 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
de7663f
Parents:
6b781c0
Message:

Improve comments for arch-specific implementations of hierarchical
4-level page tables. Improve formatting.

Files:
14 edited

Legend:

Unmodified
Added
Removed

  • boot/genarch/include/softint

    r6b781c0 rc03ee1c  
    1 ../../../kernel/genarch/include/softint/
     1../../../kernel/genarch/include/softint

  • boot/generic/genarch

    r6b781c0 rc03ee1c  
    1 ../genarch/include/
     1../genarch/include

  • kernel/arch/amd64/include/mm/page.h

    r6b781c0 rc03ee1c  
    7070}
    7171
    72 #       define KA2PA(x)      ka2pa((uintptr_t)x)
    73 #       define PA2KA_CODE(x)      (((uintptr_t) (x)) + 0xffffffff80000000)
    74 #       define PA2KA(x)      (((uintptr_t) (x)) + 0xffff800000000000)
     72#       define KA2PA(x)         ka2pa((uintptr_t) x)
     73#       define PA2KA_CODE(x)    (((uintptr_t) (x)) + 0xffffffff80000000)
     74#       define PA2KA(x)         (((uintptr_t) (x)) + 0xffff800000000000)
    7575#else
    76 #       define KA2PA(x)      ((x) - 0xffffffff80000000)
    77 #       define PA2KA(x)      ((x) + 0xffffffff80000000)
     76#       define KA2PA(x)         ((x) - 0xffffffff80000000)
     77#       define PA2KA(x)         ((x) + 0xffffffff80000000)
    7878#endif
    7979
     80/* Number of entries in each level. */
    8081#define PTL0_ENTRIES_ARCH       512
    8182#define PTL1_ENTRIES_ARCH       512
    … …  
    8384#define PTL3_ENTRIES_ARCH       512
    8485
    85 #define PTL0_SIZE_ARCH       ONE_FRAME
    86 #define PTL1_SIZE_ARCH       ONE_FRAME
    87 #define PTL2_SIZE_ARCH       ONE_FRAME
    88 #define PTL3_SIZE_ARCH       ONE_FRAME
    89 
    90 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr)>>39)&0x1ff)
    91 #define PTL1_INDEX_ARCH(vaddr)  (((vaddr)>>30)&0x1ff)
    92 #define PTL2_INDEX_ARCH(vaddr)  (((vaddr)>>21)&0x1ff)
    93 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>12)&0x1ff)
    94 
    95 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          ((pte_t *) ((((uint64_t) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 )))
    96 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          ((pte_t *) ((((uint64_t) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 )))
    97 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          ((pte_t *) ((((uint64_t) ((pte_t *)(ptl2))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl2))[(i)].addr_32_51)<<32 )))
    98 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         ((uintptr_t *) ((((uint64_t) ((pte_t *)(ptl3))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl3))[(i)].addr_32_51)<<32 )))
    99 
    100 #define SET_PTL0_ADDRESS_ARCH(ptl0)             (write_cr3((uintptr_t) (ptl0)))
    101 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       set_pt_addr((pte_t *)(ptl0), (index_t)(i), a)
    102 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)       set_pt_addr((pte_t *)(ptl1), (index_t)(i), a)
    103 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)       set_pt_addr((pte_t *)(ptl2), (index_t)(i), a)
    104 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      set_pt_addr((pte_t *)(ptl3), (index_t)(i), a)
    105 
    106 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *)(ptl0), (index_t)(i))
    107 #define GET_PTL2_FLAGS_ARCH(ptl1, i)            get_pt_flags((pte_t *)(ptl1), (index_t)(i))
    108 #define GET_PTL3_FLAGS_ARCH(ptl2, i)            get_pt_flags((pte_t *)(ptl2), (index_t)(i))
    109 #define GET_FRAME_FLAGS_ARCH(ptl3, i)           get_pt_flags((pte_t *)(ptl3), (index_t)(i))
    110 
    111 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x)         set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
    112 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)         set_pt_flags((pte_t *)(ptl1), (index_t)(i), (x))
    113 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)         set_pt_flags((pte_t *)(ptl2), (index_t)(i), (x))
    114 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)        set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
    115 
    116 #define PTE_VALID_ARCH(p)                       (*((uint64_t *) (p)) != 0)
    117 #define PTE_PRESENT_ARCH(p)                     ((p)->present != 0)
    118 #define PTE_GET_FRAME_ARCH(p)                   ((((uintptr_t)(p)->addr_12_31)<<12) | ((uintptr_t)(p)->addr_32_51<<32))
    119 #define PTE_WRITABLE_ARCH(p)                    ((p)->writeable != 0)
    120 #define PTE_EXECUTABLE_ARCH(p)                  ((p)->no_execute == 0)
     86/* Page table sizes for each level. */
     87#define PTL0_SIZE_ARCH          ONE_FRAME
     88#define PTL1_SIZE_ARCH          ONE_FRAME
     89#define PTL2_SIZE_ARCH          ONE_FRAME
     90#define PTL3_SIZE_ARCH          ONE_FRAME
     91
     92/* Macros calculating indices into page tables in each level. */
     93#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ff)
     94#define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ff)
     95#define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ff)
     96#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ff)
     97
     98/* Get PTE address accessors for each level. */
     99#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
     100        ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \
     101            (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32)))
     102#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
     103        ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \
     104            (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32)))
     105#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
     106        ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \
     107            (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32)))
     108#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
     109        ((uintptr_t *) \
     110            ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \
     111            (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32)))
     112
     113/* Set PTE address accessors for each level. */
     114#define SET_PTL0_ADDRESS_ARCH(ptl0) \
     115        (write_cr3((uintptr_t) (ptl0)))
     116#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
     117        set_pt_addr((pte_t *) (ptl0), (index_t) (i), a)
     118#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
     119        set_pt_addr((pte_t *) (ptl1), (index_t) (i), a)
     120#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
     121        set_pt_addr((pte_t *) (ptl2), (index_t) (i), a)
     122#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
     123        set_pt_addr((pte_t *) (ptl3), (index_t) (i), a)
     124
     125/* Get PTE flags accessors for each level. */
     126#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
     127        get_pt_flags((pte_t *) (ptl0), (index_t) (i))
     128#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
     129        get_pt_flags((pte_t *) (ptl1), (index_t) (i))
     130#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
     131        get_pt_flags((pte_t *) (ptl2), (index_t) (i))
     132#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
     133        get_pt_flags((pte_t *) (ptl3), (index_t) (i))
     134
     135/* Set PTE flags accessors for each level. */
     136#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
     137        set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
     138#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
     139        set_pt_flags((pte_t *) (ptl1), (index_t) (i), (x))
     140#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
     141        set_pt_flags((pte_t *) (ptl2), (index_t) (i), (x))
     142#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
     143        set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
     144
     145/* Macros for querying the last-level PTE entries. */
     146#define PTE_VALID_ARCH(p) \
     147        (*((uint64_t *) (p)) != 0)
     148#define PTE_PRESENT_ARCH(p) \
     149        ((p)->present != 0)
     150#define PTE_GET_FRAME_ARCH(p) \
     151        ((((uintptr_t) (p)->addr_12_31) << 12) | \
     152            ((uintptr_t) (p)->addr_32_51 << 32))
     153#define PTE_WRITABLE_ARCH(p) \
     154        ((p)->writeable != 0)
     155#define PTE_EXECUTABLE_ARCH(p) \
     156        ((p)->no_execute == 0)
    121157
    122158#ifndef __ASM__
    … …  
    124160/* Page fault error codes. */
    125161
    126 /** When bit on this position is 0, the page fault was caused by a not-present page. */
    127 #define PFERR_CODE_P            (1<<0) 
     162/** When bit on this position is 0, the page fault was caused by a not-present
     163 * page.
     164 */
     165#define PFERR_CODE_P            (1 << 0) 
    128166
    129167/** When bit on this position is 1, the page fault was caused by a write. */
    130 #define PFERR_CODE_RW           (1<<1)
     168#define PFERR_CODE_RW           (1 << 1)
    131169
    132170/** When bit on this position is 1, the page fault was caused in user mode. */
    133 #define PFERR_CODE_US           (1<<2)
     171#define PFERR_CODE_US           (1 << 2)
    134172
    135173/** When bit on this position is 1, a reserved bit was set in page directory. */
    136 #define PFERR_CODE_RSVD         (1<<3)
    137 
    138 /** When bit on this position os 1, the page fault was caused during instruction fecth. */
    139 #define PFERR_CODE_ID           (1<<4)
     174#define PFERR_CODE_RSVD         (1 << 3)
     175
     176/** When bit on this position os 1, the page fault was caused during instruction
     177 * fecth.
     178 */
     179#define PFERR_CODE_ID           (1 << 4)
    140180
    141181static inline int get_pt_flags(pte_t *pt, index_t i)
    … …  
    143183        pte_t *p = &pt[i];
    144184       
    145         return (
    146                 (!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
    147                 (!p->present)<<PAGE_PRESENT_SHIFT |
    148                 p->uaccessible<<PAGE_USER_SHIFT |
    149                 1<<PAGE_READ_SHIFT |
    150                 p->writeable<<PAGE_WRITE_SHIFT |
    151                 (!p->no_execute)<<PAGE_EXEC_SHIFT |
    152                 p->global<<PAGE_GLOBAL_SHIFT
    153         );
     185        return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
     186            (!p->present) << PAGE_PRESENT_SHIFT |
     187            p->uaccessible << PAGE_USER_SHIFT |
     188            1 << PAGE_READ_SHIFT |
     189            p->writeable << PAGE_WRITE_SHIFT |
     190            (!p->no_execute) << PAGE_EXEC_SHIFT |
     191            p->global << PAGE_GLOBAL_SHIFT);
    154192}
    155193

  • kernel/arch/arm32/include/mm/page.h

    r6b781c0 rc03ee1c  
    5656#ifdef KERNEL
    5757
     58/* Number of entries in each level. */
    5859#define PTL0_ENTRIES_ARCH       (2 << 12)       /* 4096 */
    5960#define PTL1_ENTRIES_ARCH       0
    6061#define PTL2_ENTRIES_ARCH       0
    61 
    6262/* coarse page tables used (256 * 4 = 1KB per page) */
    6363#define PTL3_ENTRIES_ARCH       (2 << 8)        /* 256 */
    6464
     65/* Page table sizes for each level. */
    6566#define PTL0_SIZE_ARCH          FOUR_FRAMES
    6667#define PTL1_SIZE_ARCH          0
    … …  
    6869#define PTL3_SIZE_ARCH          ONE_FRAME
    6970
     71/* Macros calculating indices into page tables for each level. */
    7072#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
    7173#define PTL1_INDEX_ARCH(vaddr)  0
    … …  
    7375#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
    7476
     77/* Get PTE address accessors for each level. */
    7578#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    7679        ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))
    … …  
    8285        ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12))
    8386
     87/* Set PTE address accessors for each level. */
    8488#define SET_PTL0_ADDRESS_ARCH(ptl0) \
    8589        (set_ptl0_addr((pte_level0_t *) (ptl0)))
    … …  
    9195        (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)
    9296
     97/* Get PTE flags accessors for each level. */
    9398#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    9499        get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i))
    … …  
    100105        get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i))
    101106
     107/* Set PTE flags accessors for each level. */
    102108#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    103109        set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x))
    … …  
    107113        set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x))
    108114
     115/* Macros for querying the last-level PTE entries. */
    109116#define PTE_VALID_ARCH(pte) \
    110117        (*((uint32_t *) (pte)) != 0)
    111118#define PTE_PRESENT_ARCH(pte) \
    112119        (((pte_level0_t *) (pte))->descriptor_type != 0)
    113 
    114 /* pte should point into ptl3 */
    115120#define PTE_GET_FRAME_ARCH(pte) \
    116121        (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)
    117 
    118 /* pte should point into ptl3 */
    119122#define PTE_WRITABLE_ARCH(pte) \
    120123        (((pte_level1_t *) (pte))->access_permission_0 == \
    121124            PTE_AP_USER_RW_KERNEL_RW)
    122 
    123125#define PTE_EXECUTABLE_ARCH(pte) \
    124126        1
    … …  
    129131typedef struct {
    130132        /* 0b01 for coarse tables, see below for details */
    131         unsigned descriptor_type     : 2;
    132         unsigned impl_specific       : 3;
    133         unsigned domain              : 4;
    134         unsigned should_be_zero      : 1;
     133        unsigned descriptor_type : 2;
     134        unsigned impl_specific : 3;
     135        unsigned domain : 4;
     136        unsigned should_be_zero : 1;
    135137
    136138        /* Pointer to the coarse 2nd level page table (holding entries for small
    … …  
    139141         * per table in comparison with 1KB per the coarse table)
    140142         */
    141         unsigned coarse_table_addr   : 22;
     143        unsigned coarse_table_addr : 22;
    142144} ATTRIBUTE_PACKED pte_level0_t;
    143145
    … …  
    146148
    147149        /* 0b10 for small pages */
    148         unsigned descriptor_type     : 2;
    149         unsigned bufferable          : 1;
    150         unsigned cacheable           : 1;
     150        unsigned descriptor_type : 2;
     151        unsigned bufferable : 1;
     152        unsigned cacheable : 1;
    151153
    152154        /* access permissions for each of 4 subparts of a page
    … …  
    156158        unsigned access_permission_2 : 2;
    157159        unsigned access_permission_3 : 2;
    158         unsigned frame_base_addr     : 20;
     160        unsigned frame_base_addr : 20;
    159161} ATTRIBUTE_PACKED pte_level1_t;
    160162
    … …  
    191193 * @param pt    Pointer to the page table to set.
    192194 */   
    193 static inline void set_ptl0_addr( pte_level0_t *pt)
     195static inline void set_ptl0_addr(pte_level0_t *pt)
    194196{
    195197        asm volatile (

  • kernel/arch/arm32/include/mm/page_fault.h

    r6b781c0 rc03ee1c  
    4242/** Decribes CP15 "fault status register" (FSR). */
    4343typedef struct {
    44         unsigned status           : 3;
    45         unsigned domain           : 4;
    46         unsigned zero             : 1;
    47         unsigned should_be_zero   : 24;
     44        unsigned status : 3;
     45        unsigned domain : 4;
     46        unsigned zero : 1;
     47        unsigned should_be_zero : 24;
    4848} ATTRIBUTE_PACKED fault_status_t;
    4949
    … …  
    6262 */
    6363typedef struct {
    64         unsigned dummy1        : 4;
    65         unsigned bit4          : 1;
    66         unsigned bits567       : 3;
    67         unsigned dummy         : 12;
    68         unsigned access        : 1;
    69         unsigned opcode        : 4;
    70         unsigned type          : 3;
    71         unsigned condition     : 4;
     64        unsigned dummy1 : 4;
     65        unsigned bit4 : 1;
     66        unsigned bits567 : 3;
     67        unsigned dummy : 12;
     68        unsigned access : 1;
     69        unsigned opcode : 4;
     70        unsigned type : 3;
     71        unsigned condition : 4;
    7272} ATTRIBUTE_PACKED instruction_t;
    7373

  • kernel/arch/ia32/include/mm/page.h

    r6b781c0 rc03ee1c  
    5757 * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
    5858 */
     59
     60/* Number of entries in each level. */
    5961#define PTL0_ENTRIES_ARCH       1024
    6062#define PTL1_ENTRIES_ARCH       0
    … …  
    6264#define PTL3_ENTRIES_ARCH       1024
    6365
    64 #define PTL0_SIZE_ARCH       ONE_FRAME
    65 #define PTL1_SIZE_ARCH       0
    66 #define PTL2_SIZE_ARCH       0
    67 #define PTL3_SIZE_ARCH       ONE_FRAME
     66/* Page table sizes for each level. */
     67#define PTL0_SIZE_ARCH          ONE_FRAME
     68#define PTL1_SIZE_ARCH          0
     69#define PTL2_SIZE_ARCH          0
     70#define PTL3_SIZE_ARCH          ONE_FRAME
    6871
     72/* Macros calculating indices for each level. */
    6973#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
    7074#define PTL1_INDEX_ARCH(vaddr)  0
    … …  
    7276#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
    7377
    74 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          ((pte_t *)((((pte_t *)(ptl0))[(i)].frame_address) << 12))
    75 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
    76 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
    77 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         ((uintptr_t)((((pte_t *)(ptl3))[(i)].frame_address) << 12))
     78/* Get PTE address accessors for each level. */
     79#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
     80        ((pte_t *) ((((pte_t *) (ptl0))[(i)].frame_address) << 12))
     81#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
     82        (ptl1)
     83#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
     84        (ptl2)
     85#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
     86        ((uintptr_t) ((((pte_t *) (ptl3))[(i)].frame_address) << 12))
    7887
    79 #define SET_PTL0_ADDRESS_ARCH(ptl0)             (write_cr3((uintptr_t) (ptl0)))
    80 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].frame_address = (a)>>12)
     88/* Set PTE address accessors for each level. */
     89#define SET_PTL0_ADDRESS_ARCH(ptl0) \
     90        (write_cr3((uintptr_t) (ptl0)))
     91#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
     92        (((pte_t *) (ptl0))[(i)].frame_address = (a) >> 12)
    8193#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    8294#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    83 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].frame_address = (a)>>12)
     95#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
     96        (((pte_t *) (ptl3))[(i)].frame_address = (a) >> 12)
    8497
    85 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *)(ptl0), (index_t)(i))
    86 #define GET_PTL2_FLAGS_ARCH(ptl1, i)            PAGE_PRESENT
    87 #define GET_PTL3_FLAGS_ARCH(ptl2, i)            PAGE_PRESENT
    88 #define GET_FRAME_FLAGS_ARCH(ptl3, i)           get_pt_flags((pte_t *)(ptl3), (index_t)(i))
     98/* Get PTE flags accessors for each level. */
     99#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
     100        get_pt_flags((pte_t *) (ptl0), (index_t) (i))
     101#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
     102        PAGE_PRESENT
     103#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
     104        PAGE_PRESENT
     105#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
     106        get_pt_flags((pte_t *) (ptl3), (index_t) (i))
    89107
    90 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x)         set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
     108/* Set PTE flags accessors for each level. */
     109#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
     110        set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
    91111#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    92112#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    93 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)        set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
     113#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
     114        set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
    94115
    95 #define PTE_VALID_ARCH(p)                       (*((uint32_t *) (p)) != 0)
    96 #define PTE_PRESENT_ARCH(p)                     ((p)->present != 0)
    97 #define PTE_GET_FRAME_ARCH(p)                   ((p)->frame_address << FRAME_WIDTH)
    98 #define PTE_WRITABLE_ARCH(p)                    ((p)->writeable != 0)
     116/* Macros for querying the last level entries. */
     117#define PTE_VALID_ARCH(p) \
     118        (*((uint32_t *) (p)) != 0)
     119#define PTE_PRESENT_ARCH(p) \
     120        ((p)->present != 0)
     121#define PTE_GET_FRAME_ARCH(p) \
     122        ((p)->frame_address << FRAME_WIDTH)
     123#define PTE_WRITABLE_ARCH(p) \
     124        ((p)->writeable != 0)
    99125#define PTE_EXECUTABLE_ARCH(p)                  1
    100126
    … …  
    106132/* Page fault error codes. */
    107133
    108 /** When bit on this position is 0, the page fault was caused by a not-present page. */
     134/** When bit on this position is 0, the page fault was caused by a not-present
     135 * page.
     136 */
    109137#define PFERR_CODE_P            (1 << 0)
    110138
    … …  
    122150        pte_t *p = &pt[i];
    123151       
    124         return (
    125                 (!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
    126                 (!p->present) << PAGE_PRESENT_SHIFT |
    127                 p->uaccessible << PAGE_USER_SHIFT |
    128                 1<<PAGE_READ_SHIFT |
    129                 p->writeable << PAGE_WRITE_SHIFT |
    130                 1<<PAGE_EXEC_SHIFT |
    131                 p->global << PAGE_GLOBAL_SHIFT
    132         );
     152        return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
     153            (!p->present) << PAGE_PRESENT_SHIFT |
     154            p->uaccessible << PAGE_USER_SHIFT |
     155            1 << PAGE_READ_SHIFT |
     156            p->writeable << PAGE_WRITE_SHIFT |
     157            1 << PAGE_EXEC_SHIFT |
     158            p->global << PAGE_GLOBAL_SHIFT);
    133159}
    134160
    … …  
    144170       
    145171        /*
    146          * Ensure that there is at least one bit set even if the present bit is cleared.
     172         * Ensure that there is at least one bit set even if the present bit is
     173         * cleared.
    147174         */
    148175        p->soft_valid = true;

  • kernel/arch/ia32xen/include/mm/page.h

    r6b781c0 rc03ee1c  
    5757 * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
    5858 */
     59
     60/* Number of entries in each level. */
    5961#define PTL0_ENTRIES_ARCH       1024
    6062#define PTL1_ENTRIES_ARCH       0
    … …  
    6264#define PTL3_ENTRIES_ARCH       1024
    6365
    64 #define PTL0_SIZE_ARCH       ONE_FRAME
    65 #define PTL1_SIZE_ARCH       0
    66 #define PTL2_SIZE_ARCH       0
    67 #define PTL3_SIZE_ARCH       ONE_FRAME
    68 
     66/* Page table size for each level. */
     67#define PTL0_SIZE_ARCH          ONE_FRAME
     68#define PTL1_SIZE_ARCH          0
     69#define PTL2_SIZE_ARCH          0
     70#define PTL3_SIZE_ARCH          ONE_FRAME
     71
     72/* Macros calculating indices into page tables in each level. */
    6973#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
    7074#define PTL1_INDEX_ARCH(vaddr)  0
    … …  
    7276#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
    7377
    74 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          ((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12))
    75 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
    76 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
    77 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))
    78 
    79 #define SET_PTL0_ADDRESS_ARCH(ptl0) { \
     78/* Get PTE address accessors for each level. */
     79#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
     80        ((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12))
     81#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
     82        (ptl1)
     83#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
     84        (ptl2)
     85#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
     86        ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))
     87
     88/* Set PTE address accessors for each level. */
     89#define SET_PTL0_ADDRESS_ARCH(ptl0) \
     90{ \
    8091        mmuext_op_t mmu_ext; \
    8192        \
    … …  
    8596}
    8697
    87 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \
     98#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
     99{ \
    88100        mmuext_op_t mmu_ext; \
    89101        \
    … …  
    101113#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    102114#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    103 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) { \
     115#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
     116{ \
    104117        mmu_update_t update; \
    105118        \
    … …  
    109122}
    110123
    111 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *) (ptl0), (index_t)(i))
    112 #define GET_PTL2_FLAGS_ARCH(ptl1, i)            PAGE_PRESENT
    113 #define GET_PTL3_FLAGS_ARCH(ptl2, i)            PAGE_PRESENT
    114 #define GET_FRAME_FLAGS_ARCH(ptl3, i)           get_pt_flags((pte_t *) (ptl3), (index_t)(i))
    115 
    116 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x)         set_pt_flags((pte_t *) (ptl0), (index_t)(i), (x))
     124/* Get PTE flags accessors for each level. */
     125#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
     126        get_pt_flags((pte_t *) (ptl0), (index_t) (i))
     127#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
     128        PAGE_PRESENT
     129#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
     130        PAGE_PRESENT
     131#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
     132        get_pt_flags((pte_t *) (ptl3), (index_t) (i))
     133
     134/* Set PTE flags accessors for each level. */
     135#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
     136        set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
    117137#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    118138#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    119 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)                set_pt_flags((pte_t *) (ptl3), (index_t)(i), (x))
    120 
    121 #define PTE_VALID_ARCH(p)                       (*((uint32_t *) (p)) != 0)
    122 #define PTE_PRESENT_ARCH(p)                     ((p)->present != 0)
    123 #define PTE_GET_FRAME_ARCH(p)                   ((p)->frame_address << FRAME_WIDTH)
    124 #define PTE_WRITABLE_ARCH(p)                    ((p)->writeable != 0)
    125 #define PTE_EXECUTABLE_ARCH(p)                  1
     139#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
     140        set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
     141
     142/* Query macros for the last level. */
     143#define PTE_VALID_ARCH(p) \
     144        (*((uint32_t *) (p)) != 0)
     145#define PTE_PRESENT_ARCH(p) \
     146        ((p)->present != 0)
     147#define PTE_GET_FRAME_ARCH(p) \
     148        ((p)->frame_address << FRAME_WIDTH)
     149#define PTE_WRITABLE_ARCH(p) \
     150        ((p)->writeable != 0)
     151#define PTE_EXECUTABLE_ARCH(p) \
     152        1
    126153
    127154#ifndef __ASM__
    … …  
    133160/* Page fault error codes. */
    134161
    135 /** When bit on this position is 0, the page fault was caused by a not-present page. */
     162/** When bit on this position is 0, the page fault was caused by a not-present
     163 * page.
     164 */
    136165#define PFERR_CODE_P            (1 << 0)
    137166
    … …  
    165194} mmuext_op_t;
    166195
    167 static inline int xen_update_va_mapping(const void *va, const pte_t pte, const unsigned int flags)
     196static inline int xen_update_va_mapping(const void *va, const pte_t pte,
     197    const unsigned int flags)
    168198{
    169199        return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags);
    170200}
    171201
    172 static inline int xen_mmu_update(const mmu_update_t *req, const unsigned int count, unsigned int *success_count, domid_t domid)
     202static inline int xen_mmu_update(const mmu_update_t *req,
     203    const unsigned int count, unsigned int *success_count, domid_t domid)
    173204{
    174205        return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid);
    175206}
    176207
    177 static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count, unsigned int *success_count, domid_t domid)
     208static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count,
     209    unsigned int *success_count, domid_t domid)
    178210{
    179211        return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid);
    … …  
    184216        pte_t *p = &pt[i];
    185217       
    186         return (
    187                 (!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
    188                 (!p->present)<<PAGE_PRESENT_SHIFT |
    189                 p->uaccessible<<PAGE_USER_SHIFT |
    190                 1<<PAGE_READ_SHIFT |
    191                 p->writeable<<PAGE_WRITE_SHIFT |
    192                 1<<PAGE_EXEC_SHIFT |
    193                 p->global<<PAGE_GLOBAL_SHIFT
    194         );
     218        return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
     219            (!p->present) << PAGE_PRESENT_SHIFT |
     220            p->uaccessible << PAGE_USER_SHIFT |
     221            1 << PAGE_READ_SHIFT |
     222            p->writeable << PAGE_WRITE_SHIFT |
     223            1 << PAGE_EXEC_SHIFT |
     224            p->global << PAGE_GLOBAL_SHIFT);
    195225}
    196226

  • kernel/arch/mips32/include/mm/page.h

    r6b781c0 rc03ee1c  
    5959 * - 32-bit virtual addresses
    6060 * - Offset is 14 bits => pages are 16K long
    61  * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
     61 * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore
     62 *   4 bytes long
    6263 * - PTE's replace EntryLo v (valid) bit with p (present) bit
    63  * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings
    64  * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared
    65  * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
     64 * - PTE's use only one bit to distinguish between cacheable and uncacheable
     65 *   mappings
     66 * - PTE's define soft_valid field to ensure there is at least one 1 bit even if
     67 *   the p bit is cleared
     68 * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable)
     69 *   and bit A (accessed)
    6670 * - PTL0 has 64 entries (6 bits)
    6771 * - PTL1 is not used
    … …  
    7074 */
    7175 
     76/* Macros describing number of entries in each level. */
    7277#define PTL0_ENTRIES_ARCH       64
    7378#define PTL1_ENTRIES_ARCH       0
    … …  
    7580#define PTL3_ENTRIES_ARCH       4096
    7681
    77 #define PTL0_SIZE_ARCH       ONE_FRAME
    78 #define PTL1_SIZE_ARCH       0
    79 #define PTL2_SIZE_ARCH       0
    80 #define PTL3_SIZE_ARCH       ONE_FRAME
     82/* Macros describing size of page tables in each level. */
     83#define PTL0_SIZE_ARCH          ONE_FRAME
     84#define PTL1_SIZE_ARCH          0
     85#define PTL2_SIZE_ARCH          0
     86#define PTL3_SIZE_ARCH          ONE_FRAME
    8187
    82 #define PTL0_INDEX_ARCH(vaddr)  ((vaddr)>>26)
    83 #define PTL1_INDEX_ARCH(vaddr)  0
    84 #define PTL2_INDEX_ARCH(vaddr)  0
    85 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>14) & 0xfff)
     88/* Macros calculating entry indices for each level. */
     89#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
     90#define PTL1_INDEX_ARCH(vaddr)  0
     91#define PTL2_INDEX_ARCH(vaddr)  0
     92#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
    8693
     94/* Set accessor for PTL0 address. */
    8795#define SET_PTL0_ADDRESS_ARCH(ptl0)
    8896
    89 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].pfn<<12)
    90 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
    91 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
    92 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].pfn<<12)
     97/* Get PTE address accessors for each level. */
     98#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
     99        (((pte_t *) (ptl0))[(i)].pfn << 12)
     100#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
     101        (ptl1)
     102#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
     103        (ptl2)
     104#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
     105        (((pte_t *) (ptl3))[(i)].pfn << 12)
    93106
    94 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
     107/* Set PTE address accessors for each level. */
     108#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
     109        (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
    95110#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    96111#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    97 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
     112#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
     113        (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
    98114
    99 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *)(ptl0), (index_t)(i))
    100 #define GET_PTL2_FLAGS_ARCH(ptl1, i)            PAGE_PRESENT
    101 #define GET_PTL3_FLAGS_ARCH(ptl2, i)            PAGE_PRESENT
    102 #define GET_FRAME_FLAGS_ARCH(ptl3, i)           get_pt_flags((pte_t *)(ptl3), (index_t)(i))
     115/* Get PTE flags accessors for each level. */
     116#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
     117        get_pt_flags((pte_t *) (ptl0), (index_t) (i))
     118#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
     119        PAGE_PRESENT
     120#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
     121        PAGE_PRESENT
     122#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
     123        get_pt_flags((pte_t *) (ptl3), (index_t) (i))
    103124
    104 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x)         set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
     125/* Set PTE flags accessors for each level. */
     126#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
     127        set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
    105128#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    106129#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    107 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)        set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
     130#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
     131        set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
    108132
     133/* Last-level info macros. */
    109134#define PTE_VALID_ARCH(pte)                     (*((uint32_t *) (pte)) != 0)
    110135#define PTE_PRESENT_ARCH(pte)                   ((pte)->p != 0)
    111 #define PTE_GET_FRAME_ARCH(pte)                 ((pte)->pfn<<12)
     136#define PTE_GET_FRAME_ARCH(pte)                 ((pte)->pfn << 12)
    112137#define PTE_WRITABLE_ARCH(pte)                  ((pte)->w != 0)
    113138#define PTE_EXECUTABLE_ARCH(pte)                1
    … …  
    122147        pte_t *p = &pt[i];
    123148       
    124         return (
    125                 (p->cacheable<<PAGE_CACHEABLE_SHIFT) |
    126                 ((!p->p)<<PAGE_PRESENT_SHIFT) |
    127                 (1<<PAGE_USER_SHIFT) |
    128                 (1<<PAGE_READ_SHIFT) |
    129                 ((p->w)<<PAGE_WRITE_SHIFT) |
    130                 (1<<PAGE_EXEC_SHIFT) |
    131                 (p->g<<PAGE_GLOBAL_SHIFT)
    132         );
    133                
     149        return ((p->cacheable << PAGE_CACHEABLE_SHIFT) |
     150            ((!p->p) << PAGE_PRESENT_SHIFT) |
     151            (1 << PAGE_USER_SHIFT) |
     152            (1 << PAGE_READ_SHIFT) |
     153            ((p->w) << PAGE_WRITE_SHIFT) |
     154            (1 << PAGE_EXEC_SHIFT) |
     155            (p->g << PAGE_GLOBAL_SHIFT));
    134156}
    135157

  • kernel/arch/ppc32/include/mm/page.h

    r6b781c0 rc03ee1c  
    3333 */
    3434
    35 #ifndef __ppc32_PAGE_H__
    36 #define __ppc32_PAGE_H__
     35#ifndef KERN_ppc32_PAGE_H_
     36#define KERN_ppc32_PAGE_H_
    3737
    3838#include <arch/mm/frame.h>
    … …  
    6666 */
    6767
     68/* Number of entries in each level. */
    6869#define PTL0_ENTRIES_ARCH       1024
    6970#define PTL1_ENTRIES_ARCH       0
    … …  
    7172#define PTL3_ENTRIES_ARCH       1024
    7273
    73 #define PTL0_SIZE_ARCH       ONE_FRAME
    74 #define PTL1_SIZE_ARCH       0
    75 #define PTL2_SIZE_ARCH       0
    76 #define PTL3_SIZE_ARCH       ONE_FRAME
     74/* Page table sizes for each level. */
     75#define PTL0_SIZE_ARCH          ONE_FRAME
     76#define PTL1_SIZE_ARCH          0
     77#define PTL2_SIZE_ARCH          0
     78#define PTL3_SIZE_ARCH          ONE_FRAME
    7779
     80/* Macros calculating indices into page tables on each level. */
    7881#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
    7982#define PTL1_INDEX_ARCH(vaddr)  0
    … …  
    8184#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
    8285
    83 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *) (ptl0))[(i)].pfn << 12)
    84 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
    85 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
    86 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *) (ptl3))[(i)].pfn << 12)
     86/* Get PTE address accessors for each level. */
     87#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
     88        (((pte_t *) (ptl0))[(i)].pfn << 12)
     89#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
     90        (ptl1)
     91#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
     92        (ptl2)
     93#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
     94        (((pte_t *) (ptl3))[(i)].pfn << 12)
    8795
     96/* Set PTE address accessors for each level. */
    8897#define SET_PTL0_ADDRESS_ARCH(ptl0)
    89 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
     98#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
     99        (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
    90100#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    91101#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    92 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
     102#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
     103        (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
    93104
    94 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *) (ptl0), (index_t) (i))
    95 #define GET_PTL2_FLAGS_ARCH(ptl1, i)            PAGE_PRESENT
    96 #define GET_PTL3_FLAGS_ARCH(ptl2, i)            PAGE_PRESENT
    97 #define GET_FRAME_FLAGS_ARCH(ptl3, i)           get_pt_flags((pte_t *) (ptl3), (index_t) (i))
     105/* Get PTE flags accessors for each level. */
     106#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
     107        get_pt_flags((pte_t *) (ptl0), (index_t) (i))
     108#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
     109        PAGE_PRESENT
     110#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
     111        PAGE_PRESENT
     112#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
     113        get_pt_flags((pte_t *) (ptl3), (index_t) (i))
    98114
    99 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x)         set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
     115/* Set PTE flags accessors for each level. */
     116#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
     117        set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
    100118#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    101119#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    102 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)        set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
     120#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
     121        set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
    103122
     123/* Macros for querying the last-level PTEs. */
    104124#define PTE_VALID_ARCH(pte)                     (*((uint32_t *) (pte)) != 0)
    105125#define PTE_PRESENT_ARCH(pte)                   ((pte)->p != 0)
    … …  
    117137        pte_t *p = &pt[i];
    118138       
    119         return (
    120                 (1 << PAGE_CACHEABLE_SHIFT) |
    121                 ((!p->p) << PAGE_PRESENT_SHIFT) |
    122                 (1 << PAGE_USER_SHIFT) |
    123                 (1 << PAGE_READ_SHIFT) |
    124                 (1 << PAGE_WRITE_SHIFT) |
    125                 (1 << PAGE_EXEC_SHIFT) |
    126                 (p->g << PAGE_GLOBAL_SHIFT)
    127         );
     139        return ((1 << PAGE_CACHEABLE_SHIFT) |
     140            ((!p->p) << PAGE_PRESENT_SHIFT) |
     141            (1 << PAGE_USER_SHIFT) |
     142            (1 << PAGE_READ_SHIFT) |
     143            (1 << PAGE_WRITE_SHIFT) |
     144            (1 << PAGE_EXEC_SHIFT) |
     145            (p->g << PAGE_GLOBAL_SHIFT));
    128146}
    129147

  • kernel/arch/ppc64/include/mm/page.h

    r6b781c0 rc03ee1c  
    6666 */
    6767
     68/* Number of entries in each level. */
    6869#define PTL0_ENTRIES_ARCH       1024
    6970#define PTL1_ENTRIES_ARCH       0
    … …  
    7172#define PTL3_ENTRIES_ARCH       1024
    7273
     74/* Sizes of page tables in each level. */
    7375#define PTL0_SIZE_ARCH          ONE_FRAME
    7476#define PTL1_SIZE_ARCH          0
    … …  
    7678#define PTL3_SIZE_ARCH          ONE_FRAME
    7779
     80/* Macros calculating indices into page tables in each level. */
    7881#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
    7982#define PTL1_INDEX_ARCH(vaddr)  0
    … …  
    8184#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
    8285
    83 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *) (ptl0))[(i)].pfn << 12)
    84 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
    85 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
    86 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *) (ptl3))[(i)].pfn << 12)
     86/* Get PTE address accessors for each level. */
     87#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
     88        (((pte_t *) (ptl0))[(i)].pfn << 12)
     89#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
     90        (ptl1)
     91#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
     92        (ptl2)
     93#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
     94        (((pte_t *) (ptl3))[(i)].pfn << 12)
    8795
     96/* Set PTE address accessors for each level. */
    8897#define SET_PTL0_ADDRESS_ARCH(ptl0)
    89 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
     98#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
     99        (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
    90100#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    91101#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    92 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
     102#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
     103        (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
    93104
    94 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *) (ptl0), (index_t) (i))
    95 #define GET_PTL2_FLAGS_ARCH(ptl1, i)            PAGE_PRESENT
    96 #define GET_PTL3_FLAGS_ARCH(ptl2, i)            PAGE_PRESENT
    97 #define GET_FRAME_FLAGS_ARCH(ptl3, i)           get_pt_flags((pte_t *) (ptl3), (index_t) (i))
     105/* Get PTE flags accessors for each level. */
     106#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
     107        get_pt_flags((pte_t *) (ptl0), (index_t) (i))
     108#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
     109        PAGE_PRESENT
     110#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
     111        PAGE_PRESENT
     112#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
     113        get_pt_flags((pte_t *) (ptl3), (index_t) (i))
    98114
    99 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x)         set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
     115/* Set PTE flags accessors for each level. */
     116#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
     117        set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
    100118#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    101119#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    102 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)        set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
     120#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
     121        set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
    103122
     123/* Macros for querying the last-level PTEs. */
    104124#define PTE_VALID_ARCH(pte)                     (*((uint32_t *) (pte)) != 0)
    105125#define PTE_PRESENT_ARCH(pte)                   ((pte)->p != 0)
    … …  
    117137        pte_t *p = &pt[i];
    118138       
    119         return (
    120                 (1 << PAGE_CACHEABLE_SHIFT) |
    121                 ((!p->p) << PAGE_PRESENT_SHIFT) |
    122                 (1 << PAGE_USER_SHIFT) |
    123                 (1 << PAGE_READ_SHIFT) |
    124                 (1 << PAGE_WRITE_SHIFT) |
    125                 (1 << PAGE_EXEC_SHIFT) |
    126                 (p->g << PAGE_GLOBAL_SHIFT)
    127         );
     139        return ((1 << PAGE_CACHEABLE_SHIFT) |
     140            ((!p->p) << PAGE_PRESENT_SHIFT) |
     141            (1 << PAGE_USER_SHIFT) |
     142            (1 << PAGE_READ_SHIFT) |
     143            (1 << PAGE_WRITE_SHIFT) |
     144            (1 << PAGE_EXEC_SHIFT) |
     145            (p->g << PAGE_GLOBAL_SHIFT));
    128146}
    129147

  • kernel/genarch/include/mm/page_ht.h

    r6b781c0 rc03ee1c  
    5151
    5252#define PAGE_HT_ENTRIES_BITS    13
    53 #define PAGE_HT_ENTRIES         (1<<PAGE_HT_ENTRIES_BITS)
     53#define PAGE_HT_ENTRIES         (1 << PAGE_HT_ENTRIES_BITS)
    5454
     55/* Macros for querying page hash table PTEs. */
    5556#define PTE_VALID(pte)          ((pte) != NULL)
    5657#define PTE_PRESENT(pte)        ((pte)->p != 0)

  • kernel/genarch/include/mm/page_pt.h

    r6b781c0 rc03ee1c  
    8383
    8484/*
    85  * These macros are provided to change shape of the 4-level
    86  * tree of page tables on respective level.
     85 * These macros are provided to change the shape of the 4-level tree of page
     86 * tables on respective level.
    8787 */
    8888#define SET_PTL1_ADDRESS(ptl0, i, a)    SET_PTL1_ADDRESS_ARCH(ptl0, i, a)
    … …  
    107107#define SET_FRAME_FLAGS(ptl3, i, x)     SET_FRAME_FLAGS_ARCH(ptl3, i, x)
    108108
     109/*
     110 * Macros for querying the last-level PTEs.
     111 */
    109112#define PTE_VALID(p)            PTE_VALID_ARCH((p))
    110113#define PTE_PRESENT(p)          PTE_PRESENT_ARCH((p))
    … …  
    119122extern page_mapping_operations_t pt_mapping_operations;
    120123
    121 extern void page_mapping_insert_pt(as_t *as, uintptr_t page, uintptr_t frame, int flags);
     124extern void page_mapping_insert_pt(as_t *as, uintptr_t page, uintptr_t frame,
     125    int flags);
    122126extern pte_t *page_mapping_find_pt(as_t *as, uintptr_t page);
    123127

  • kernel/generic/src/mm/backend_elf.c

    r6b781c0 rc03ee1c  
    327327                                btree_insert(&area->sh_info->pagemap,
    328328                                    (base + j * PAGE_SIZE) - area->base,
    329                                         (void *) PTE_GET_FRAME(pte), NULL);
     329                                    (void *) PTE_GET_FRAME(pte), NULL);
    330330                                page_table_unlock(area->as, false);
    331331

  • kernel/generic/src/syscall/syscall.c

    r6b781c0 rc03ee1c  
    9393
    9494/** Dispatch system call */
    95 unative_t syscall_handler(unative_t a1, unative_t a2, unative_t a3,
    96                          unative_t a4, unative_t id)
     95unative_t syscall_handler(unative_t a1, unative_t a2, unative_t a3, unative_t a4,
     96    unative_t id)
    9797{
    9898        unative_t rc;
    … …  
    101101                rc = syscall_table[id](a1, a2, a3, a4);
    102102        else {
    103                 klog_printf("TASK %llu: Unknown syscall id %d",TASK->taskid,id);
     103                klog_printf("TASK %llu: Unknown syscall id %d", TASK->taskid,
     104                    id);
    104105                task_kill(TASK->taskid);
    105106                thread_exit();
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