Changeset c058a388 in mainline
- Timestamp:
- 2017-07-16T17:19:37Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- fe5db713
- Parents:
- 7bd99bf
- Location:
- uspace/drv/bus/usb/xhci
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/commands.c
r7bd99bf rc058a388 46 46 static inline int ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target) 47 47 { 48 assert(hc); 48 49 uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7)); 49 50 pio_write_32(&hc->db_arry[doorbell], v); … … 54 55 unsigned doorbell, unsigned target) 55 56 { 57 assert(hc); 58 assert(trb); 59 56 60 xhci_trb_ring_enqueue(&hc->command_ring, trb); 57 61 ring_doorbell(hc, doorbell, target); … … 116 120 int xhci_send_no_op_command(xhci_hc_t *hc) 117 121 { 122 assert(hc); 123 118 124 xhci_trb_t trb; 119 125 memset(&trb, 0, sizeof(trb)); … … 126 132 int xhci_send_enable_slot_command(xhci_hc_t *hc) 127 133 { 134 assert(hc); 135 128 136 xhci_trb_t trb; 129 137 memset(&trb, 0, sizeof(trb)); … … 138 146 int xhci_send_disable_slot_command(xhci_hc_t *hc, uint32_t slot_id) 139 147 { 148 assert(hc); 149 140 150 xhci_trb_t trb; 141 151 memset(&trb, 0, sizeof(trb)); … … 151 161 xhci_input_ctx_t *ictx) 152 162 { 163 assert(hc); 164 assert(ictx); 165 153 166 /** 154 167 * TODO: Requirements for this command: … … 161 174 162 175 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx); 163 trb.parameter = host2xhci(32, phys_addr & 0xFFFFFFFFFFFFFFF0);176 trb.parameter = host2xhci(32, phys_addr & (~0xF)); 164 177 165 178 /** … … 180 193 xhci_input_ctx_t *ictx) 181 194 { 195 assert(hc); 196 assert(ictx); 197 182 198 xhci_trb_t trb; 183 199 memset(&trb, 0, sizeof(trb)); 184 200 185 201 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx); 186 trb.parameter = host2xhci(32, phys_addr & 0xFFFFFFFFFFFFFFF0);202 trb.parameter = host2xhci(32, phys_addr & (~0xF)); 187 203 188 204 trb.control = host2xhci(32, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD << 10); … … 196 212 xhci_input_ctx_t *ictx) 197 213 { 214 assert(hc); 215 assert(ictx); 216 198 217 /** 199 218 * Note: All Drop Context flags of the input context shall be 0, … … 206 225 207 226 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx); 208 trb.parameter = host2xhci(32, phys_addr & 0xFFFFFFFFFFFFFFF0);227 trb.parameter = host2xhci(32, phys_addr & (~0xF)); 209 228 210 229 trb.control = host2xhci(32, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD << 10); … … 217 236 int xhci_send_reset_endpoint_command(xhci_hc_t *hc, uint32_t slot_id, uint32_t ep_id, uint8_t tcs) 218 237 { 238 assert(hc); 239 219 240 /** 220 241 * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for … … 235 256 int xhci_send_stop_endpoint_command(xhci_hc_t *hc, uint32_t slot_id, uint32_t ep_id, uint8_t susp) 236 257 { 258 assert(hc); 259 237 260 xhci_trb_t trb; 238 261 memset(&trb, 0, sizeof(trb)); … … 245 268 246 269 return enqueue_trb(hc, &trb, 0, 0); 247 270 } 271 272 int xhci_send_reset_device_command(xhci_hc_t *hc, uint32_t slot_id) 273 { 274 assert(hc); 275 276 xhci_trb_t trb; 277 memset(&trb, 0, sizeof(trb)); 278 279 trb.control = host2xhci(32, XHCI_TRB_TYPE_RESET_DEVICE_CMD << 10); 280 trb.control |= host2xhci(32, hc->command_ring.pcs); 281 trb.control |= host2xhci(32, slot_id << 24); 282 283 return enqueue_trb(hc, &trb, 0, 0); 248 284 } 249 285 250 286 int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb) 251 287 { 288 assert(hc); 289 assert(trb); 290 252 291 usb_log_debug("HC(%p) Command completed.", hc); 253 292 xhci_dump_trb(trb); … … 290 329 // handle it appropriately! 291 330 return EOK; 331 case XHCI_TRB_TYPE_RESET_DEVICE_CMD: 332 return EOK; 292 333 default: 293 334 usb_log_debug2("Unsupported command trb."); -
uspace/drv/bus/usb/xhci/commands.h
r7bd99bf rc058a388 49 49 int xhci_send_reset_endpoint_command(xhci_hc_t *, uint32_t, uint32_t, uint8_t); 50 50 int xhci_send_stop_endpoint_command(xhci_hc_t *, uint32_t, uint32_t, uint8_t); 51 // TODO: Set dequeue ptr (section 4.6.10). 52 int xhci_send_reset_device_command(xhci_hc_t *, uint32_t); 53 // TODO: Force event (optional normative, for VMM, section 4.6.12). 54 // TODO: Negotiate bandwidth (optional normative, section 4.6.13). 55 // TODO: Set latency tolerance value (optional normative, section 4.6.14). 56 // TODO: Get port bandwidth (mandatory, but needs root hub implementation, section 4.6.15). 57 // TODO: Force header (mandatory, but needs root hub implementation, section 4.6.16). 51 58 52 59 int xhci_handle_command_completion(xhci_hc_t *, xhci_trb_t *);
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