Changes in kernel/arch/ppc32/src/mm/tlb.c [a000878c:c15b374] in mainline
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kernel/arch/ppc32/src/mm/tlb.c (modified) (21 diffs)
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kernel/arch/ppc32/src/mm/tlb.c
ra000878c rc15b374 45 45 46 46 static unsigned int seed = 10; 47 static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;48 47 static unsigned int seed_real 48 __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; 49 49 50 50 /** Try to find PTE for faulting address 51 51 * 52 * Try to find PTE for faulting address. 53 * The as->lock must be held on entry to this function 54 * if lock is true. 55 * 56 * @param as Address space. 57 * @param lock Lock/unlock the address space. 58 * @param badvaddr Faulting virtual address. 59 * @param access Access mode that caused the fault. 60 * @param istate Pointer to interrupted state. 61 * @param pfrc Pointer to variable where as_page_fault() return code 62 * will be stored. 63 * @return PTE on success, NULL otherwise. 64 * 65 */ 66 static pte_t * 67 find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, 52 * @param as Address space. 53 * @param lock Lock/unlock the address space. 54 * @param badvaddr Faulting virtual address. 55 * @param access Access mode that caused the fault. 56 * @param istate Pointer to interrupted state. 57 * @param pfrc Pointer to variable where as_page_fault() return code 58 * will be stored. 59 * 60 * @return PTE on success, NULL otherwise. 61 * 62 */ 63 static pte_t *find_mapping_and_check(as_t *as, uintptr_t badvaddr, int access, 68 64 istate_t *istate, int *pfrc) 69 65 { 66 ASSERT(mutex_locked(&as->lock)); 67 70 68 /* 71 69 * Check if the mapping exists in page tables. 72 */ 70 */ 73 71 pte_t *pte = page_mapping_find(as, badvaddr); 74 72 if ((pte) && (pte->present)) { … … 79 77 return pte; 80 78 } else { 81 int rc;82 83 79 /* 84 80 * Mapping not found in page tables. 85 81 * Resort to higher-level page fault handler. 86 82 */ 87 page_table_unlock(as, lock); 88 switch (rc = as_page_fault(badvaddr, access, istate)) { 83 page_table_unlock(as, true); 84 85 int rc = as_page_fault(badvaddr, access, istate); 86 switch (rc) { 89 87 case AS_PF_OK: 90 88 /* … … 92 90 * The mapping ought to be in place. 93 91 */ 94 page_table_lock(as, lock);92 page_table_lock(as, true); 95 93 pte = page_mapping_find(as, badvaddr); 96 94 ASSERT((pte) && (pte->present)); … … 98 96 return pte; 99 97 case AS_PF_DEFER: 100 page_table_lock(as, lock);98 page_table_lock(as, true); 101 99 *pfrc = rc; 102 100 return NULL; 103 101 case AS_PF_FAULT: 104 page_table_lock(as, lock);102 page_table_lock(as, true); 105 103 *pfrc = rc; 106 104 return NULL; 107 105 default: 108 106 panic("Unexpected rc (%d).", rc); 109 } 110 } 111 } 112 107 } 108 } 109 } 113 110 114 111 static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) 115 112 { 116 const char *symbol = symtab_fmt_name_lookup(istate->pc); 117 const char *sym2 = symtab_fmt_name_lookup(istate->lr); 118 119 fault_if_from_uspace(istate, 120 "PHT Refill Exception on %p.", badvaddr); 121 panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, 122 istate->pc, symbol, sym2); 123 } 124 113 fault_if_from_uspace(istate, "PHT Refill Exception on %p.", badvaddr); 114 panic_memtrap(istate, PF_ACCESS_UNKNOWN, badvaddr, 115 "PHT Refill Exception."); 116 } 125 117 126 118 static void pht_insert(const uintptr_t vaddr, const pte_t *pte) … … 129 121 uint32_t api = (vaddr >> 22) & 0x3f; 130 122 131 uint32_t vsid; 132 asm volatile ( 133 "mfsrin %0, %1\n" 134 : "=r" (vsid) 135 : "r" (vaddr) 136 ); 137 138 uint32_t sdr1; 139 asm volatile ( 140 "mfsdr1 %0\n" 141 : "=r" (sdr1) 142 ); 123 uint32_t vsid = sr_get(vaddr); 124 uint32_t sdr1 = sdr1_get(); 125 126 // FIXME: compute size of PHT exactly 143 127 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); 144 128 … … 215 199 } 216 200 217 218 201 /** Process Instruction/Data Storage Exception 219 202 * … … 222 205 * 223 206 */ 224 void pht_refill(int n, istate_t *istate) 225 { 207 void pht_refill(unsigned int n, istate_t *istate) 208 { 209 as_t *as = (AS == NULL) ? AS_KERNEL : AS; 226 210 uintptr_t badvaddr; 227 pte_t *pte;228 int pfrc;229 as_t *as;230 bool lock;231 232 if (AS == NULL) {233 as = AS_KERNEL;234 lock = false;235 } else {236 as = AS;237 lock = true;238 }239 211 240 212 if (n == VECTOR_DATA_STORAGE) … … 242 214 else 243 215 badvaddr = istate->pc; 244 245 page_table_lock(as, lock); 246 247 pte = find_mapping_and_check(as, lock, badvaddr, 216 217 page_table_lock(as, true); 218 219 int pfrc; 220 pte_t *pte = find_mapping_and_check(as, badvaddr, 248 221 PF_ACCESS_READ /* FIXME */, istate, &pfrc); 222 249 223 if (!pte) { 250 224 switch (pfrc) { … … 257 231 * or copy_to_uspace(). 258 232 */ 259 page_table_unlock(as, lock);233 page_table_unlock(as, true); 260 234 return; 261 235 default: … … 264 238 } 265 239 266 pte->accessed = 1; /* Record access to PTE */ 240 /* Record access to PTE */ 241 pte->accessed = 1; 267 242 pht_insert(badvaddr, pte); 268 243 269 page_table_unlock(as, lock);244 page_table_unlock(as, true); 270 245 return; 271 246 272 247 fail: 273 page_table_unlock(as, lock);248 page_table_unlock(as, true); 274 249 pht_refill_fail(badvaddr, istate); 275 250 } 276 277 251 278 252 /** Process Instruction/Data Storage Exception in Real Mode … … 282 256 * 283 257 */ 284 bool pht_refill_real( int n, istate_t *istate)258 bool pht_refill_real(unsigned int n, istate_t *istate) 285 259 { 286 260 uintptr_t badvaddr; … … 291 265 badvaddr = istate->pc; 292 266 293 uint32_t physmem; 294 asm volatile ( 295 "mfsprg3 %0\n" 296 : "=r" (physmem) 297 ); 267 uint32_t physmem = physmem_top(); 298 268 299 269 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) … … 303 273 uint32_t api = (badvaddr >> 22) & 0x3f; 304 274 305 uint32_t vsid; 306 asm volatile ( 307 "mfsrin %0, %1\n" 308 : "=r" (vsid) 309 : "r" (badvaddr) 310 ); 311 312 uint32_t sdr1; 313 asm volatile ( 314 "mfsdr1 %0\n" 315 : "=r" (sdr1) 316 ); 275 uint32_t vsid = sr_get(badvaddr); 276 uint32_t sdr1 = sdr1_get(); 277 278 // FIXME: compute size of PHT exactly 317 279 phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); 318 280 … … 396 358 } 397 359 398 399 360 /** Process ITLB/DTLB Miss Exception in Real Mode 400 361 * 401 362 * 402 363 */ 403 void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) 364 void tlb_refill_real(unsigned int n, uint32_t tlbmiss, ptehi_t ptehi, 365 ptelo_t ptelo, istate_t *istate) 404 366 { 405 367 uint32_t badvaddr = tlbmiss & 0xfffffffc; 406 407 uint32_t physmem; 408 asm volatile ( 409 "mfsprg3 %0\n" 410 : "=r" (physmem) 411 ); 368 uint32_t physmem = physmem_top(); 412 369 413 370 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) … … 420 377 uint32_t index = 0; 421 378 asm volatile ( 422 "mtspr 981, % 0\n"423 "mtspr 982, % 1\n"424 "tlbld % 2\n"425 "tlbli % 2\n"426 : "=r" (index)427 : "r" (ptehi),428 "r" (ptelo)379 "mtspr 981, %[ptehi]\n" 380 "mtspr 982, %[ptelo]\n" 381 "tlbld %[index]\n" 382 "tlbli %[index]\n" 383 : [index] "=r" (index) 384 : [ptehi] "r" (ptehi), 385 [ptelo] "r" (ptelo) 429 386 ); 430 387 } 431 388 432 433 389 void tlb_arch_init(void) 434 390 { … … 436 392 } 437 393 438 439 394 void tlb_invalidate_all(void) 440 395 { 441 396 uint32_t index; 397 442 398 asm volatile ( 443 "li % 0, 0\n"399 "li %[index], 0\n" 444 400 "sync\n" 445 401 446 402 ".rept 64\n" 447 " tlbie %0\n"448 " addi %0, %0, 0x1000\n"403 " tlbie %[index]\n" 404 " addi %[index], %[index], 0x1000\n" 449 405 ".endr\n" 450 406 … … 452 408 "tlbsync\n" 453 409 "sync\n" 454 : "=r" (index)410 : [index] "=r" (index) 455 411 ); 456 412 } 457 413 458 459 414 void tlb_invalidate_asid(asid_t asid) 460 415 { 461 uint32_t sdr1; 462 asm volatile ( 463 "mfsdr1 %0\n" 464 : "=r" (sdr1) 465 ); 416 uint32_t sdr1 = sdr1_get(); 417 418 // FIXME: compute size of PHT exactly 466 419 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); 467 420 468 uint32_t i;421 size_t i; 469 422 for (i = 0; i < 8192; i++) { 470 423 if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && … … 472 425 phte[i].v = 0; 473 426 } 427 474 428 tlb_invalidate_all(); 475 429 } 476 477 430 478 431 void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) … … 482 435 } 483 436 484 485 437 #define PRINT_BAT(name, ureg, lreg) \ 486 438 asm volatile ( \ 487 "mfspr %0," #ureg "\n" \ 488 "mfspr %1," #lreg "\n" \ 489 : "=r" (upper), "=r" (lower) \ 439 "mfspr %[upper], " #ureg "\n" \ 440 "mfspr %[lower], " #lreg "\n" \ 441 : [upper] "=r" (upper), \ 442 [lower] "=r" (lower) \ 490 443 ); \ 444 \ 491 445 mask = (upper & 0x1ffc) >> 2; \ 492 446 if (upper & 3) { \ 493 447 uint32_t tmp = mask; \ 494 448 length = 128; \ 449 \ 495 450 while (tmp) { \ 496 451 if ((tmp & 1) == 0) { \ … … 503 458 } else \ 504 459 length = 0; \ 460 \ 505 461 printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ 506 462 sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ … … 515 471 516 472 for (sr = 0; sr < 16; sr++) { 517 uint32_t vsid; 518 asm volatile ( 519 "mfsrin %0, %1\n" 520 : "=r" (vsid) 521 : "r" (sr << 28) 522 ); 473 uint32_t vsid = sr_get(sr << 28); 474 523 475 printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, 524 476 sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
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