Changeset c52ed6b in mainline for arch/sparc64/include/barrier.h

Timestamp:

2005-12-12T23:55:08Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5bb8e45

Parents:

0bd4f56d

Message:

sparc64 work.
More ITLB and DTLB controlling functions.

File:

• arch/sparc64/include/barrier.h (modified) (1 diff)

arch/sparc64/include/barrier.h

@@ -40 +40 @@
 #define write_barrier()
 
-#define flush()                 __asm__ volatile ("flush\n" ::: "memory")
+/** Flush Instruction Memory. */
+static inline void flush(void)
+{
+        /*
+         * The FLUSH instruction takes address parameter,
+         * but JPS1 implementations are free to ignore it.
+         * The only requirement is that it is a valid address
+         * as it is passed to D-MMU.
+         */
+        __asm__ volatile ("flush %sp\n");       /* %sp is guaranteed to reference mapped memory */
+}
 
 #endif