Changeset c685fc8 in mainline


Ignore:
Timestamp:
2010-07-01T20:50:31Z (15 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
6dce6af
Parents:
75c9852
Message:

cstyle

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/src/asm.S

    r75c9852 rc685fc8  
    1 #
    2 # Copyright (c) 2007 Michal Kebrt
    3 # All rights reserved.
    4 #
    5 # Redistribution and use in source and binary forms, with or without
    6 # modification, are permitted provided that the following conditions
    7 # are met:
    8 #
    9 # - Redistributions of source code must retain the above copyright
    10 #   notice, this list of conditions and the following disclaimer.
    11 # - Redistributions in binary form must reproduce the above copyright
    12 #   notice, this list of conditions and the following disclaimer in the
    13 #   documentation and/or other materials provided with the distribution.
    14 # - The name of the author may not be used to endorse or promote products
    15 #   derived from this software without specific prior written permission.
    16 #
    17 # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
    18 # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
    19 # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
    20 # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
    21 # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
    22 # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
    26 # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    27 #
     1/*
     2 * Copyright (c) 2007 Michal Kebrt
     3 * All rights reserved.
     4 *
     5 * Redistribution and use in source and binary forms, with or without
     6 * modification, are permitted provided that the following conditions
     7 * are met:
     8 *
     9 * - Redistributions of source code must retain the above copyright
     10 *   notice, this list of conditions and the following disclaimer.
     11 * - Redistributions in binary form must reproduce the above copyright
     12 *   notice, this list of conditions and the following disclaimer in the
     13 *   documentation and/or other materials provided with the distribution.
     14 * - The name of the author may not be used to endorse or promote products
     15 *   derived from this software without specific prior written permission.
     16 *
     17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27 */
    2828
    29        
    3029.text
    3130
    … …  
    4746memcpy_from_uspace:
    4847memcpy_to_uspace:
    49         add     r3, r1, #3
    50         bic     r3, r3, #3
    51         cmp     r1, r3
    52         stmdb   sp!, {r4, r5, lr}
    53         mov     r5, r0                  /* save dst */
    54         beq     4f
    55 1:
    56         cmp     r2, #0
    57         movne   ip, #0
    58         beq     3f
    59 2:
    60         ldrb    r3, [ip, r1]
    61         strb    r3, [ip, r0]
    62         add     ip, ip, #1
    63         cmp     ip, r2
    64         bne     2b
    65 3:
    66         mov     r0, r5
    67         ldmia   sp!, {r4, r5, pc}
    68 4:
    69         add     r3, r0, #3
    70         bic     r3, r3, #3
    71         cmp     r0, r3
    72         bne     1b
    73         movs    r4, r2, lsr #2
    74         moveq   lr, r4
    75         beq     6f
    76         mov     lr, #0
    77         mov     ip, lr
    78 5:
    79         ldr     r3, [ip, r1]
    80         add     lr, lr, #1
    81         cmp     lr, r4
    82         str     r3, [ip, r0]
    83         add     ip, ip, #4
    84         bne     5b
    85 6:
    86         ands    r4, r2, #3
    87         beq     3b
    88         mov     r3, lr, lsl #2
    89         add     r0, r3, r0
    90         add     ip, r3, r1
    91         mov     r2, #0
    92 7:
    93         ldrb    r3, [r2, ip]
    94         strb    r3, [r2, r0]
    95         add     r2, r2, #1
    96         cmp     r2, r4
    97         bne     7b
    98         b       3b
     48        add r3, r1, #3
     49        bic r3, r3, #3
     50        cmp r1, r3
     51        stmdb sp!, {r4, r5, lr}
     52        mov r5, r0 /* save dst */
     53        beq 4f
     54       
     55        1:
     56                cmp r2, #0
     57                movne ip, #0
     58                beq 3f
     59       
     60        2:
     61                ldrb r3, [ip, r1]
     62                strb r3, [ip, r0]
     63                add ip, ip, #1
     64                cmp ip, r2
     65                bne 2b
     66       
     67        3:
     68                mov r0, r5
     69                ldmia sp!, {r4, r5, pc}
     70       
     71        4:
     72                add r3, r0, #3
     73                bic r3, r3, #3
     74                cmp r0, r3
     75                bne 1b
     76                movs r4, r2, lsr #2
     77                moveq lr, r4
     78                beq 6f
     79                mov lr, #0
     80                mov ip, lr
     81       
     82        5:
     83                ldr r3, [ip, r1]
     84                add lr, lr, #1
     85                cmp lr, r4
     86                str r3, [ip, r0]
     87                add ip, ip, #4
     88                bne 5b
     89       
     90        6:
     91                ands r4, r2, #3
     92                beq 3b
     93                mov r3, lr, lsl #2
     94                add r0, r3, r0
     95                add ip, r3, r1
     96                mov r2, #0
     97       
     98        7:
     99                ldrb r3, [r2, ip]
     100                strb r3, [r2, r0]
     101                add r2, r2, #1
     102                cmp r2, r4
     103                bne 7b
     104                b 3b
    99105
    100106memcpy_from_uspace_failover_address:
    101107memcpy_to_uspace_failover_address:
    102         mov     r0, #0
    103         ldmia   sp!, {r4, r5, pc}
     108        mov r0, #0
     109        ldmia sp!, {r4, r5, pc}
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