Changes in boot/arch/arm32/src/mm.c [b5a3b50:c6b601b] in mainline
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boot/arch/arm32/src/mm.c
rb5a3b50 rc6b601b 38 38 #include <arch/mm.h> 39 39 40 /** Check if caching can be enabled for a given memory section.41 *42 * Memory areas used for I/O are excluded from caching.43 * At the moment caching is enabled only on GTA02.44 *45 * @param section The section number.46 *47 * @return 1 if the given section can be mapped as cacheable, 0 otherwise.48 */49 static inline int section_cacheable(pfn_t section)50 {51 #ifdef MACHINE_gta0252 unsigned long address = section << PTE_SECTION_SHIFT;53 54 if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)55 return 0;56 else57 return 1;58 #else59 return 0;60 #endif61 }62 63 40 /** Initialize "section" page table entry. 64 41 * … … 78 55 pte->descriptor_type = PTE_DESCRIPTOR_SECTION; 79 56 pte->bufferable = 1; 80 pte->cacheable = section_cacheable(frame);57 pte->cacheable = 0; 81 58 pte->xn = 0; 82 59 pte->domain = 0; … … 146 123 "ldr r1, =0x00000005\n" 147 124 #else 148 #ifdef MACHINE_gta02149 /* Mask to enable paging (bit 0),150 D-cache (bit 2), I-cache (bit 12) */151 "ldr r1, =0x00001005\n"152 #else153 125 /* Mask to enable paging */ 154 126 "ldr r1, =0x00000001\n" 155 #endif156 127 #endif 157 128 "orr r0, r0, r1\n"
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