Changeset c711efe in mainline

Timestamp:

2008-06-15T08:21:17Z (17 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

1eb154f

Parents:

0af4f9e

Message:

On sparc64, when the operand to the FLUSH instruction doesn't matter, the
instruction's semantics is to flush the pipeline.

Location:

kernel/arch/sparc64/include

Files:

• barrier.h (modified) (1 diff)
• mm/tlb.h (modified) (7 diffs)

kernel/arch/sparc64/include/barrier.h

@@ -61 +61 @@
         asm volatile ("flush %0\n" :: "r" ((a)) : "memory")
 
-/** Flush Instruction Memory instruction. */
-static inline void flush_blind(void)
+/** Flush Instruction pipeline. */
+static inline void flush_pipeline(void)
 {
         /*

kernel/arch/sparc64/include/mm/tlb.h

@@ -161 +161 @@
 {
         asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
-        flush_blind();
+        flush_pipeline();
 }
 
@@ -180 +180 @@
 {
         asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
-        flush_blind();
+        flush_pipeline();
 }
 
@@ -210 +210 @@
         reg.tlb_entry = entry;
         asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
-        flush_blind();
+        flush_pipeline();
 }
 
@@ -280 +280 @@
 {
         asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
-        flush_blind();
+        flush_pipeline();
 }
 
@@ -319 +319 @@
 {
         asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
-        flush_blind();
+        flush_pipeline();
 }
 
@@ -348 +348 @@
 {
         asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
-        flush_blind();
+        flush_pipeline();
 }
 
@@ -401 +401 @@
                                                          * address within the
                                                          * ASI */ 
-        flush_blind();
+        flush_pipeline();
 }