Changeset c7ec94a4 in mainline for arch/ia64/src/mm/page.c

Timestamp:

2006-02-06T14:18:28Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f5935ed

Parents:

214f5bb

Message:

Page hash table architectures now use generic hash table to manage
mappings.

File:

• arch/ia64/src/mm/page.c (modified) (14 diffs)

arch/ia64/src/mm/page.c

@@ -43 +43 @@
 #include <memstr.h>
 
-static void set_vhpt_environment(void);
+static void set_environment(void);
 
 /** Initialize ia64 virtual address translation subsystem. */
@@ -50 +50 @@
         page_operations = &page_ht_operations;
         pk_disable();
-        set_vhpt_environment();
+        set_environment();
 }
 
 /** Initialize VHPT and region registers. */
-void set_vhpt_environment(void)
+void set_environment(void)
 {
         region_register rr;
@@ -88 +88 @@
 
         /*
-         * Allocate VHPT and invalidate all its entries.
-         */
-        page_ht = (pte_t *) frame_alloc(VHPT_WIDTH - FRAME_WIDTH, FRAME_KA);
-        memsetb((__address) page_ht, VHPT_SIZE, 0);
-        ht_invalidate_all();    
-        
-        /*
          * Set up PTA register.
          */
@@ -101 +94 @@
         pta.map.vf = 1;                   /* large entry format */
         pta.map.size = VHPT_WIDTH;
-        pta.map.base = ((__address) page_ht) >> PTA_BASE_SHIFT;
+        pta.map.base = VHPT_BASE >> PTA_BASE_SHIFT;
         pta_write(pta.word);
         srlz_i();
@@ -114 +107 @@
  * @param asid Address space identifier.
  *
- * @return Head of VHPT collision chain for page and asid.
- */
-pte_t *vhpt_hash(__address page, asid_t asid)
+ * @return VHPT entry address.
+ */
+vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
 {
         region_register rr_save, rr;
         index_t vrn;
         rid_t rid;
-        pte_t *t;
+        vhpt_entry_t *v;
 
         vrn = page >> VRN_SHIFT;
@@ -131 +124 @@
                  * The RID is already in place, compute thash and return.
                  */
-                t = (pte_t *) thash(page);
-                return t;
+                v = (vhpt_entry_t *) thash(page);
+                return v;
         }
         
@@ -143 +136 @@
         rr_write(vrn, rr.word);
         srlz_i();
-        t = (pte_t *) thash(page);
+        v = (vhpt_entry_t *) thash(page);
         rr_write(vrn, rr_save.word);
         srlz_i();
         srlz_d();
 
-        return t;
+        return v;
 }
 
@@ -160 +153 @@
  * @return True if page and asid match the page and asid of t, false otherwise.
  */
-bool vhpt_compare(__address page, asid_t asid, pte_t *t)
+bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
 {
         region_register rr_save, rr;    
@@ -167 +160 @@
         bool match;
 
-        ASSERT(t);
+        ASSERT(v);
 
         vrn = page >> VRN_SHIFT;
@@ -177 +170 @@
                  * The RID is already in place, compare ttag with t and return.
                  */
-                return ttag(page) == t->present.tag.tag_word;
+                return ttag(page) == v->present.tag.tag_word;
         }
         
@@ -188 +181 @@
         rr_write(vrn, rr.word);
         srlz_i();
-        match = (ttag(page) == t->present.tag.tag_word);
+        match = (ttag(page) == v->present.tag.tag_word);
         rr_write(vrn, rr_save.word);
         srlz_i();
@@ -204 +197 @@
  * @param flags Different flags for the mapping.
  */
-void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags)
+void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
 {
         region_register rr_save, rr;    
@@ -211 +204 @@
         __u64 tag;
 
-        ASSERT(t);
+        ASSERT(v);
 
         vrn = page >> VRN_SHIFT;
@@ -232 +225 @@
          * Clear the entry.
          */
-        t->word[0] = 0;
-        t->word[1] = 0;
-        t->word[2] = 0;
-        t->word[3] = 0;
-        
-        t->present.p = true;
-        t->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
-        t->present.a = false;   /* not accessed */
-        t->present.d = false;   /* not dirty */
-        t->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
-        t->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
-        t->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0; 
-        t->present.ppn = frame >> PPN_SHIFT;
-        t->present.ed = false;  /* exception not deffered */
-        t->present.ps = PAGE_WIDTH;
-        t->present.key = 0;
-        t->present.tag.tag_word = tag;
-        t->present.next = NULL;
-}
+        v->word[0] = 0;
+        v->word[1] = 0;
+        v->word[2] = 0;
+        v->word[3] = 0;
+        
+        v->present.p = true;
+        v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
+        v->present.a = false;   /* not accessed */
+        v->present.d = false;   /* not dirty */
+        v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
+        v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
+        v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0; 
+        v->present.ppn = frame >> PPN_SHIFT;
+        v->present.ed = false;  /* exception not deffered */
+        v->present.ps = PAGE_WIDTH;
+        v->present.key = 0;
+        v->present.tag.tag_word = tag;
+}