Changeset c9b8c5c in mainline

Timestamp:

2005-04-24T21:59:33Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ad36bd6

Parents:

f07bba5

Message:

APIC changes and fixes.
Be more robust during MP configuration.

Do not use APIC ID as CPU_ID_ARCH anymore.
Changing APIC ID's is not a good idea.
Use dr0 register instead.

Files:

• arch/ia32/include/asm.h (modified) (1 diff)
• arch/ia32/include/cpu.h (modified) (1 diff)
• arch/ia32/include/smp/apic.h (modified) (1 diff)
• arch/ia32/src/asm.s (modified) (1 diff)
• arch/ia32/src/ia32.c (modified) (1 diff)
• arch/ia32/src/interrupt.c (modified) (1 diff)
• arch/ia32/src/smp/apic.c (modified) (6 diffs)
• arch/ia32/src/smp/mp.c (modified) (3 diffs)
• src/Makefile.config (modified) (1 diff)
• src/main/main.c (modified) (1 diff)

arch/ia32/include/asm.h

@@ -59 +59 @@
 extern void cpu_sleep(void);
 
+extern void write_dr0(__u32 v);
+extern __u32 read_dr0(void);
+
 #endif

arch/ia32/include/cpu.h

@@ -35 +35 @@
 
 #ifdef __SMP__
-#define CPU_ID_ARCH     ((config.cpu_active>1)?l_apic_id():0)
+#define CPU_ID_ARCH     (read_dr0())
 #else
 #define CPU_ID_ARCH     (0)

arch/ia32/include/smp/apic.h

@@ -99 +99 @@
 #define L_APIC_IDMask   0xf
 
+/* Local APIC Version Register */
+#define LAVR            (0x030/sizeof(__u32))
+#define LAVR_Mask       0xff
+#define is_local_apic(x)        (((x)&LAVR_Mask&0xf0)==0x1)
+#define is_82489DX_apic(x)      ((((x)&LAVR_Mask&0xf0)==0x0))
+#define is_local_xapic(x)       (((x)&LAVR_Mask)==0x14)
+
 /* IO APIC */
 #define IOREGSEL        (0x00/sizeof(__u32))

arch/ia32/src/asm.s

@@ -53 +53 @@
 .global memsetw
 .global memcmp
+.global write_dr0
+.global read_dr0
+
+write_dr0:
+        pushl %eax
+        movl 8(%esp),%eax
+        movl %eax,%dr0
+        popl %eax
+        ret
+        
+read_dr0:
+        movl %dr0,%eax
+        ret
 
 #

arch/ia32/src/ia32.c

@@ -50 +50 @@
         pm_init();
 
+        write_dr0(config.cpu_active - 1);
+
         if (config.cpu_active == 1) {
                 i8042_init();   /* a20 bit */

arch/ia32/src/interrupt.c

@@ -93 +93 @@
 {
         printf("cpu%d: syscall\n", CPU->id);
-        thread_usleep(600);
+        thread_usleep(1000000);
 }
 

arch/ia32/src/smp/apic.c

@@ -104 +104 @@
         }
 
-
-
         /*
          * Configure the BSP's lapic.
@@ -184 +182 @@
         l_apic[ICRhi] = hi;
         l_apic[ICRlo] = lo;
-        
+
         /*
          * According to MP Specification, 20us should be enough to
@@ -196 +194 @@
         if (lo & SEND_PENDING)
                 printf("IPI is pending.\n");
-        
+
         l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
 
@@ -204 +202 @@
         delay(10000);
 
-        /*
-         * MP specification says this should not be done for 82489DX-based
-         * l_apic's. However, everything is ok as long as STARTUP IPI is ignored
-         * by 8249DX.
-         */
-        for (i = 0; i < 2; i++) {
-                lo = l_apic[ICRlo] & ICRloClear;
-                lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
-                l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST |  TRGRMODE_LEVEL;
-                delay(200);
-        }
+        if (!is_82489DX_apic(l_apic[LAVR])) {
+                /*
+                 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
+                 */
+                for (i = 0; i<2; i++) {
+                        lo = l_apic[ICRlo] & ICRloClear;
+                        lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
+                        l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST |  TRGRMODE_LEVEL;
+                        delay(200);
+                }
+        }
+        
         
         return apic_poll_errors();
@@ -222 +221 @@
 {
         __u32 tmp, t1, t2;
-        int cpu_id = config.cpu_active - 1;
-        
-
-        /*
-         * Here we set local APIC ID's so that they match operating system's CPU ID's
-         * This operation is dangerous as it is model specific.
-         * TODO: some care should be taken.
-         * NOTE: CPU may not be used to define APIC ID
-         */
-        if (l_apic_id() != cpu_id) {
-                l_apic[L_APIC_ID] &= L_APIC_IDClear;
-                l_apic[L_APIC_ID] |= (l_apic[L_APIC_ID]&L_APIC_IDClear)|((cpu_id)<<L_APIC_IDShift);
-        }
 
         l_apic[LVT_Err] |= (1<<16);
@@ -245 +231 @@
         l_apic[TPR] &= TPRClear;
 
-        if (CPU->arch.family >= 6)
-                enable_l_apic_in_msr();
+//      if (CPU->arch.family >= 6)
+//              enable_l_apic_in_msr();
         
         tmp = l_apic[ICRlo] & ICRloClear;

arch/ia32/src/smp/mp.c

@@ -487 +487 @@
                 if (pr[i].cpu_flags & (1<<0) == 0)
                         continue;
-        
+
                 /*
                  * The bootstrap processor is already up.
@@ -493 +493 @@
                 if (pr[i].cpu_flags & (1<<1))
                         continue;
+
+                if (pr[i].l_apic_id == l_apic_id()) {
+                        printf("%X: bad processor entry #%d, will not send IPI to myself\n", &pr[i], i);
+                        continue;
+                }
                 
                 /*
@@ -502 +507 @@
                 memcopy(gdt, gdt_new, GDT_ITEMS*sizeof(struct descriptor));
                 gdtr.base = (__address) gdt_new;
-                
+
                 if (l_apic_send_init_ipi(pr[i].l_apic_id)) {
                         /*

src/Makefile.config

@@ -23 +23 @@
 #TEST_DIR=synch/rwlock2/
 #TEST_DIR=synch/rwlock3/
-TEST_DIR=synch/rwlock4/
-#TEST_DIR=synch/rwlock5/
+#TEST_DIR=synch/rwlock4/
+TEST_DIR=synch/rwlock5/
 #TEST_DIR=synch/semaphore1/
 #TEST_DIR=synch/semaphore2/

src/main/main.c

@@ -119 +119 @@
         mp_init();      /* Multiprocessor */
         #endif /* __SMP__ */
+        
+        printf("config.cpu_count=%d\n", config.cpu_count);
 
         cpu_init();