Changeset c9b8c5c in mainline for arch/ia32/src/smp/apic.c

Timestamp:

2005-04-24T21:59:33Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ad36bd6

Parents:

f07bba5

Message:

APIC changes and fixes.
Be more robust during MP configuration.

Do not use APIC ID as CPU_ID_ARCH anymore.
Changing APIC ID's is not a good idea.
Use dr0 register instead.

File:

• arch/ia32/src/smp/apic.c (modified) (6 diffs)

arch/ia32/src/smp/apic.c

@@ -104 +104 @@
         }
 
-
-
         /*
          * Configure the BSP's lapic.
@@ -184 +182 @@
         l_apic[ICRhi] = hi;
         l_apic[ICRlo] = lo;
-        
+
         /*
          * According to MP Specification, 20us should be enough to
@@ -196 +194 @@
         if (lo & SEND_PENDING)
                 printf("IPI is pending.\n");
-        
+
         l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
 
@@ -204 +202 @@
         delay(10000);
 
-        /*
-         * MP specification says this should not be done for 82489DX-based
-         * l_apic's. However, everything is ok as long as STARTUP IPI is ignored
-         * by 8249DX.
-         */
-        for (i = 0; i < 2; i++) {
-                lo = l_apic[ICRlo] & ICRloClear;
-                lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
-                l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST |  TRGRMODE_LEVEL;
-                delay(200);
-        }
+        if (!is_82489DX_apic(l_apic[LAVR])) {
+                /*
+                 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
+                 */
+                for (i = 0; i<2; i++) {
+                        lo = l_apic[ICRlo] & ICRloClear;
+                        lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
+                        l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST |  TRGRMODE_LEVEL;
+                        delay(200);
+                }
+        }
+        
         
         return apic_poll_errors();
@@ -222 +221 @@
 {
         __u32 tmp, t1, t2;
-        int cpu_id = config.cpu_active - 1;
-        
-
-        /*
-         * Here we set local APIC ID's so that they match operating system's CPU ID's
-         * This operation is dangerous as it is model specific.
-         * TODO: some care should be taken.
-         * NOTE: CPU may not be used to define APIC ID
-         */
-        if (l_apic_id() != cpu_id) {
-                l_apic[L_APIC_ID] &= L_APIC_IDClear;
-                l_apic[L_APIC_ID] |= (l_apic[L_APIC_ID]&L_APIC_IDClear)|((cpu_id)<<L_APIC_IDShift);
-        }
 
         l_apic[LVT_Err] |= (1<<16);
@@ -245 +231 @@
         l_apic[TPR] &= TPRClear;
 
-        if (CPU->arch.family >= 6)
-                enable_l_apic_in_msr();
+//      if (CPU->arch.family >= 6)
+//              enable_l_apic_in_msr();
         
         tmp = l_apic[ICRlo] & ICRloClear;