Changeset cc205f1 in mainline
- Timestamp:
- 2005-10-06T12:45:22Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- fd3c9e5
- Parents:
- bca1b47
- Files:
-
- 1 added
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
Makefile.config
rbca1b47 rcc205f1 41 41 #TEST_DIR=print/print1/ 42 42 #TEST_DIR=thread/thread1/ 43 #TEST_DIR=mm/mapping1/ -
arch/ia32/src/mm/tlb.c
rbca1b47 rcc205f1 28 28 29 29 #include <mm/tlb.h> 30 #include <arch/mm/asid.h> 30 31 #include <arch/asm.h> 31 32 32 void tlb_invalidate(int asid) 33 /** Invalidate all TLB entries 34 * 35 * Invalidate all TLB entries. 36 * 37 * @param asid This argument is ignored. 38 */ 39 void tlb_invalidate(asid_t asid) 33 40 { 34 41 write_cr3(read_cr3()); -
arch/mips32/include/mm/asid.h
rbca1b47 rcc205f1 31 31 32 32 #include <arch/types.h> 33 #include <typedefs.h> 34 35 #define ASIDS 256 36 #define ASID_INVALID 0 37 #define ASID_START 1 33 38 34 39 typedef __u8 asid_t; … … 36 41 extern asid_t asid_get(void); 37 42 extern void asid_put(asid_t asid); 43 extern bool asid_has_conflicts(asid_t asid); 38 44 39 45 #endif -
arch/mips32/include/mm/tlb.h
rbca1b47 rcc205f1 42 42 #define PAGE_CACHEABLE_EXC_WRITE 5 43 43 44 struct entry_lo { 45 unsigned g : 1; /* global bit */ 46 unsigned v : 1; /* valid bit */ 47 unsigned d : 1; /* dirty/write-protect bit */ 48 unsigned c : 3; /* cache coherency attribute */ 49 unsigned pfn : 24; /* frame number */ 50 unsigned zero: 2; /* zero */ 51 } __attribute__ ((packed)); 44 union entry_lo { 45 struct { 46 unsigned g : 1; /* global bit */ 47 unsigned v : 1; /* valid bit */ 48 unsigned d : 1; /* dirty/write-protect bit */ 49 unsigned c : 3; /* cache coherency attribute */ 50 unsigned pfn : 24; /* frame number */ 51 unsigned zero: 2; /* zero */ 52 } __attribute__ ((packed)); 53 __u32 value; 54 }; 52 55 53 56 struct pte { … … 61 64 } __attribute__ ((packed)); 62 65 63 struct entry_hi { 64 unsigned asid : 8; 65 unsigned : 5; 66 unsigned vpn2 : 19; 67 } __attribute__ ((packed)); 66 union entry_hi { 67 struct { 68 unsigned asid : 8; 69 unsigned : 5; 70 unsigned vpn2 : 19; 71 } __attribute__ ((packed)); 72 __u32 value; 73 }; 68 74 69 struct page_mask { 70 unsigned : 13; 71 unsigned mask : 12; 72 unsigned : 7; 73 } __attribute__ ((packed)); 75 union page_mask { 76 struct { 77 unsigned : 13; 78 unsigned mask : 12; 79 unsigned : 7; 80 } __attribute__ ((packed)); 81 __u32 value; 82 }; 74 83 75 struct index { 76 unsigned index : 4; 77 unsigned : 27; 78 unsigned p : 1; 79 } __attribute__ ((packed)); 84 union index { 85 struct { 86 unsigned index : 4; 87 unsigned : 27; 88 unsigned p : 1; 89 } __attribute__ ((packed)); 90 __u32 value; 91 }; 92 93 typedef union entry_lo entry_lo_t; 94 typedef union entry_hi entry_hi_t; 95 typedef union page_mask page_mask_t; 96 typedef union index tlb_index_t; 80 97 81 98 /** Probe TLB for Matching Entry -
arch/mips32/src/mm/asid.c
rbca1b47 rcc205f1 1 1 /* 2 2 * Copyright (C) 2005 Martin Decky 3 * Copyright (C) 2005 Jakub Jermar 3 4 * All rights reserved. 4 5 * … … 31 32 #include <arch.h> 32 33 #include <debug.h> 33 34 #define ASIDS 256 34 #include <typedefs.h> 35 35 36 36 static spinlock_t asid_usage_lock; … … 54 54 spinlock_lock(&asid_usage_lock); 55 55 56 for (i =0, j = 0; (i<ASIDS); i++) {56 for (i = ASID_START, j = ASID_START; i < ASIDS; i++) { 57 57 if (asid_usage[i] < min) { 58 58 j = i; … … 63 63 } 64 64 65 asid_usage[ i]++;65 asid_usage[j]++; 66 66 67 67 spinlock_unlock(&asid_usage_lock); … … 84 84 spinlock_lock(&asid_usage_lock); 85 85 86 ASSERT(asid != ASID_INVALID); 87 86 88 ASSERT(asid_usage[asid] > 0); 87 89 asid_usage[asid]--; … … 90 92 cpu_priority_restore(pri); 91 93 } 94 95 /** Find out whether ASID is used by more address spaces 96 * 97 * Find out whether ASID is used by more address spaces. 98 * 99 * @param asid ASID in question. 100 * 101 * @return True if 'asid' is used by more address spaces, false otherwise. 102 */ 103 bool asid_has_conflicts(asid_t asid) 104 { 105 bool has_conflicts = false; 106 pri_t pri; 107 108 ASSERT(asid != ASID_INVALID); 109 110 pri = cpu_priority_high(); 111 spinlock_lock(&asid_usage_lock); 112 113 if (asid_usage[asid] > 1) 114 has_conflicts = true; 115 116 spinlock_unlock(&asid_usage_lock); 117 cpu_priority_restore(pri); 118 119 return has_conflicts; 120 } -
arch/mips32/src/mm/tlb.c
rbca1b47 rcc205f1 38 38 #include <synch/spinlock.h> 39 39 #include <print.h> 40 #include <debug.h> 40 41 41 42 static void tlb_refill_fail(struct exception_regdump *pstate); … … 44 45 45 46 static pte_t *find_mapping_and_check(__address badvaddr); 46 static void prepare_entry_lo( struct entry_lo*lo, bool g, bool v, bool d, int c, __address pfn);47 static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn); 47 48 48 49 /** Initialize TLB … … 83 84 void tlb_refill(struct exception_regdump *pstate) 84 85 { 85 struct entry_lolo;86 entry_lo_t lo; 86 87 __address badvaddr; 87 88 pte_t *pte; … … 105 106 */ 106 107 if ((badvaddr/PAGE_SIZE) % 2 == 0) { 107 cp0_entry_lo0_write( *((__u32 *) &lo));108 cp0_entry_lo0_write(lo.value); 108 109 cp0_entry_lo1_write(0); 109 110 } 110 111 else { 111 112 cp0_entry_lo0_write(0); 112 cp0_entry_lo1_write( *((__u32 *) &lo));113 cp0_entry_lo1_write(lo.value); 113 114 } 114 115 tlbwr(); … … 130 131 void tlb_invalid(struct exception_regdump *pstate) 131 132 { 132 struct indexindex;133 tlb_index_t index; 133 134 __address badvaddr; 134 struct entry_lolo;135 entry_lo_t lo; 135 136 pte_t *pte; 136 137 … … 141 142 */ 142 143 tlbp(); 143 *((__u32 *) &index)= cp0_index_read();144 index.value = cp0_index_read(); 144 145 145 146 spinlock_lock(&VM->lock); … … 148 149 * Fail if the entry is not in TLB. 149 150 */ 150 if (index.p) 151 goto fail; 151 if (index.p) { 152 printf("TLB entry not found.\n"); 153 goto fail; 154 } 152 155 153 156 pte = find_mapping_and_check(badvaddr); … … 171 174 */ 172 175 if ((badvaddr/PAGE_SIZE) % 2 == 0) 173 cp0_entry_lo0_write( *((__u32 *) &lo));176 cp0_entry_lo0_write(lo.value); 174 177 else 175 cp0_entry_lo1_write( *((__u32 *) &lo));178 cp0_entry_lo1_write(lo.value); 176 179 tlbwi(); 177 180 … … 190 193 * @param pstate Interrupted register context. 191 194 */ 192 193 195 void tlb_modified(struct exception_regdump *pstate) 194 196 { 195 struct indexindex;197 tlb_index_t index; 196 198 __address badvaddr; 197 struct entry_lolo;199 entry_lo_t lo; 198 200 pte_t *pte; 199 201 … … 204 206 */ 205 207 tlbp(); 206 *((__u32 *) &index)= cp0_index_read();208 index.value = cp0_index_read(); 207 209 208 210 spinlock_lock(&VM->lock); … … 211 213 * Fail if the entry is not in TLB. 212 214 */ 213 if (index.p) 214 goto fail; 215 if (index.p) { 216 printf("TLB entry not found.\n"); 217 goto fail; 218 } 215 219 216 220 pte = find_mapping_and_check(badvaddr); … … 241 245 */ 242 246 if ((badvaddr/PAGE_SIZE) % 2 == 0) 243 cp0_entry_lo0_write( *((__u32 *) &lo));247 cp0_entry_lo0_write(lo.value); 244 248 else 245 cp0_entry_lo1_write( *((__u32 *) &lo));249 cp0_entry_lo1_write(lo.value); 246 250 tlbwi(); 247 251 … … 289 293 } 290 294 291 292 void tlb_invalidate(int asid) 293 { 295 /** Invalidate TLB entries with specified ASID 296 * 297 * Invalidate TLB entries with specified ASID. 298 * 299 * @param asid ASID. 300 */ 301 void tlb_invalidate(asid_t asid) 302 { 303 entry_hi_t hi; 294 304 pri_t pri; 295 305 int i; 306 307 ASSERT(asid != ASID_INVALID); 308 296 309 pri = cpu_priority_high(); 297 310 298 // TODO 311 for (i = 0; i < TLB_SIZE; i++) { 312 cp0_index_write(i); 313 tlbr(); 314 315 hi.value = cp0_entry_hi_read(); 316 if (hi.asid == asid) { 317 cp0_pagemask_write(TLB_PAGE_MASK_16K); 318 cp0_entry_hi_write(0); 319 cp0_entry_lo0_write(0); 320 cp0_entry_lo1_write(0); 321 tlbwi(); 322 } 323 } 299 324 300 325 cpu_priority_restore(pri); … … 312 337 pte_t *find_mapping_and_check(__address badvaddr) 313 338 { 314 struct entry_hihi;339 entry_hi_t hi; 315 340 pte_t *pte; 316 341 317 *((__u32 *) &hi)= cp0_entry_hi_read();342 hi.value = cp0_entry_hi_read(); 318 343 319 344 /* 320 345 * Handler cannot succeed if the ASIDs don't match. 321 346 */ 322 if (hi.asid != VM->asid) 347 if (hi.asid != VM->asid) { 348 printf("EntryHi.asid=%d, VM->asid=%d\n", hi.asid, VM->asid); 323 349 return NULL; 350 } 324 351 325 352 /* … … 327 354 */ 328 355 pte = find_mapping(badvaddr, 0); 329 if (!pte) 356 if (!pte) { 357 printf("No such mapping.\n"); 330 358 return NULL; 359 } 331 360 332 361 /* 333 362 * Handler cannot succeed if the mapping is marked as invalid. 334 363 */ 335 if (!pte->v) 364 if (!pte->v) { 365 printf("Invalid mapping.\n"); 336 366 return NULL; 367 } 337 368 338 369 return pte; 339 370 } 340 371 341 void prepare_entry_lo( struct entry_lo*lo, bool g, bool v, bool d, int c, __address pfn)372 void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn) 342 373 { 343 374 lo->g = g; -
arch/mips32/src/mm/vm.c
rbca1b47 rcc205f1 32 32 #include <arch/cp0.h> 33 33 #include <arch.h> 34 #include <print.h>35 34 36 35 /** Install ASID of the current VM … … 42 41 void vm_install_arch(vm_t *vm) 43 42 { 44 struct entry_hihi;43 entry_hi_t hi; 45 44 pri_t pri; 46 45 47 *((__u32 *) &hi)= cp0_entry_hi_read();46 hi.value = cp0_entry_hi_read(); 48 47 49 48 pri = cpu_priority_high(); -
include/mm/tlb.h
rbca1b47 rcc205f1 30 30 #define __TLB_H__ 31 31 32 #include <arch/mm/asid.h> 33 32 34 extern void tlb_init(void); 33 35 … … 44 46 /* Export TLB interface that each architecture must implement. */ 45 47 extern void tlb_init_arch(void); 46 extern void tlb_invalidate( int asid);48 extern void tlb_invalidate(asid_t asid); 47 49 extern void tlb_shootdown_ipi_send(void); 48 50
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