Changeset ccc362a1 in mainline
- Timestamp:
- 2017-08-21T18:46:34Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6c742f5e
- Parents:
- c16479e
- Location:
- kernel/arch/riscv64
- Files:
-
- 10 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/riscv64/include/arch/arch.h
rc16479e rccc362a1 38 38 #include <arch/boot/boot.h> 39 39 40 extern void riscv64_pre_main(bootinfo_t *); 41 40 42 #endif 41 43 -
kernel/arch/riscv64/include/arch/mm/asid.h
rc16479e rccc362a1 42 42 typedef uint32_t asid_t; 43 43 44 #define asid_get() (ASID_START + 1) 45 #define asid_put(asid) 46 44 47 #endif 45 48 -
kernel/arch/riscv64/include/arch/mm/frame.h
rc16479e rccc362a1 43 43 #ifndef __ASM__ 44 44 45 #include <arch/boot/boot.h> 46 47 extern uintptr_t physmem_start; 48 extern uintptr_t htif_frame; 49 extern uintptr_t pt_frame; 50 extern memmap_t memmap; 51 45 52 extern void frame_low_arch_init(void); 46 53 extern void frame_high_arch_init(void); -
kernel/arch/riscv64/include/arch/mm/km.h
rc16479e rccc362a1 39 39 #include <stddef.h> 40 40 41 #define KM_RISCV64_IDENTITY_START UINT64_C(0xffff800000000000) 42 #define KM_RISCV64_IDENTITY_SIZE UINT64_C(0x0000400000000000) 43 44 #define KM_RISCV64_NON_IDENTITY_START UINT64_C(0xffffc00000000000) 45 #define KM_RISCV64_NON_IDENTITY_SIZE UINT64_C(0x0000400000000000) 46 41 47 extern void km_identity_arch_init(void); 42 48 extern void km_non_identity_arch_init(void); -
kernel/arch/riscv64/include/arch/mm/page.h
rc16479e rccc362a1 50 50 51 51 /* 52 * Page table entry types.53 *54 * - PTE_TYPE_PTR: pointer to next level PTE55 * - PTE_TYPE_PTR_GLOBAL: pointer to next level PTE (global mapping)56 *57 * - PTE_TYPE_SRURX: kernel read, user read execute58 * - PTE_TYPE_SRWURWX: kernel read write, user read write execute59 * - PTE_TYPE_SRUR: kernel read, user read60 * - PTE_TYPE_SRWURW: kernel read write, user read write61 * - PTE_TYPE_SRXURX: kernel read execute, user read execute62 * - PTE_TYPE_SRWXURWX: kernel read write execute, user read write execute63 *64 * - PTE_TYPE_SR: kernel read65 * - PTE_TYPE_SRW: kernel read write66 * - PTE_TYPE_SRX: kernel read execute67 * - PTE_TYPE_SRWX: kernel read write execute68 *69 * - PTE_TYPE_SR_GLOBAL: kernel read (global mapping)70 * - PTE_TYPE_SRW_GLOBAL: kernel read write (global mapping)71 * - PTE_TYPE_SRX_GLOBAL: kernel read execute (global mapping)72 * - PTE_TYPE_SRWX_GLOBAL: kernel read write execute (global mapping)73 */74 75 #define PTE_TYPE_PTR 076 #define PTE_TYPE_PTR_GLOBAL 177 78 #define PTE_TYPE_SRURX 279 #define PTE_TYPE_SRWURWX 380 #define PTE_TYPE_SRUR 481 #define PTE_TYPE_SRWURW 582 #define PTE_TYPE_SRXURX 683 #define PTE_TYPE_SRWXURWX 784 85 #define PTE_TYPE_SR 886 #define PTE_TYPE_SRW 987 #define PTE_TYPE_SRX 1088 #define PTE_TYPE_SRWX 1189 90 #define PTE_TYPE_SR_GLOBAL 1291 #define PTE_TYPE_SRW_GLOBAL 1392 #define PTE_TYPE_SRX_GLOBAL 1493 #define PTE_TYPE_SRWX_GLOBAL 1594 95 /*96 52 * Implementation of 4-level page table interface. 97 53 * … … 125 81 #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff) 126 82 83 /* Flags mask for non-leaf page table entries */ 84 #define NON_LEAF_MASK (~(PAGE_READ | PAGE_WRITE | PAGE_EXEC)) 85 127 86 /* Get PTE address accessors for each level. */ 128 87 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ … … 139 98 140 99 /* Set PTE address accessors for each level. */ 141 #define SET_PTL0_ADDRESS_ARCH(ptl0) 100 #define SET_PTL0_ADDRESS_ARCH(ptl0) \ 101 (write_satp((uintptr_t) (ptl0))) 142 102 143 103 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ … … 167 127 168 128 /* Set PTE flags accessors for each level. */ 169 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \170 set_pt_flags((pte_t *) (ptl0), (size_t) (i), ( x))171 172 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \173 set_pt_flags((pte_t *) (ptl1), (size_t) (i), ( x))174 175 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \176 set_pt_flags((pte_t *) (ptl2), (size_t) (i), ( x))177 178 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \179 set_pt_flags((pte_t *) (ptl3), (size_t) (i), ( x))129 #define SET_PTL1_FLAGS_ARCH(ptl0, i, flags) \ 130 set_pt_flags((pte_t *) (ptl0), (size_t) (i), ((flags) & NON_LEAF_MASK)) 131 132 #define SET_PTL2_FLAGS_ARCH(ptl1, i, flags) \ 133 set_pt_flags((pte_t *) (ptl1), (size_t) (i), ((flags) & NON_LEAF_MASK)) 134 135 #define SET_PTL3_FLAGS_ARCH(ptl2, i, flags) \ 136 set_pt_flags((pte_t *) (ptl2), (size_t) (i), ((flags) & NON_LEAF_MASK)) 137 138 #define SET_FRAME_FLAGS_ARCH(ptl3, i, flags) \ 139 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (flags)) 180 140 181 141 /* Set PTE present accessors for each level. */ … … 196 156 #define PTE_PRESENT_ARCH(pte) ((pte)->valid != 0) 197 157 #define PTE_GET_FRAME_ARCH(pte) ((uintptr_t) (pte)->pfn << 12) 198 199 #define PTE_WRITABLE_ARCH(pte) \ 200 (((pte)->type == PTE_TYPE_SRWURWX) || \ 201 ((pte)->type == PTE_TYPE_SRWURW) || \ 202 ((pte)->type == PTE_TYPE_SRWXURWX)) 203 204 #define PTE_EXECUTABLE_ARCH(pte) \ 205 (((pte)->type == PTE_TYPE_SRURX) || \ 206 ((pte)->type == PTE_TYPE_SRWURWX) || \ 207 ((pte)->type == PTE_TYPE_SRXURX) || \ 208 ((pte)->type == PTE_TYPE_SRWXURWX)) 158 #define PTE_WRITABLE_ARCH(pte) ((pte)->writable != 0) 159 #define PTE_EXECUTABLE_ARCH(pte) ((pte)->executable != 0) 209 160 210 161 #ifndef __ASM__ … … 217 168 typedef struct { 218 169 unsigned long valid : 1; /**< Valid bit. */ 219 unsigned long type : 4; /**< Entry type. */ 220 unsigned long referenced : 1; /**< Refenced bit. */ 170 unsigned long readable : 1; /**< Readable bit. */ 171 unsigned long writable : 1; /**< Writable bit. */ 172 unsigned long executable : 1; /**< Executable bit. */ 173 unsigned long user : 1; /**< User mode accessible bit. */ 174 unsigned long global : 1; /**< Global mapping bit. */ 175 unsigned long accessed : 1; /**< Accessed bit. */ 221 176 unsigned long dirty : 1; /**< Dirty bit. */ 222 unsigned long reserved : 3; /**< Reserved bits. */177 unsigned long reserved : 2; /**< Reserved bits. */ 223 178 unsigned long pfn : 54; /**< Physical frame number. */ 224 179 } pte_t; … … 229 184 230 185 return (((!entry->valid) << PAGE_PRESENT_SHIFT) | 231 ( (entry->type < PTE_TYPE_SR)<< PAGE_USER_SHIFT) |232 PAGE_READ|233 ( PTE_WRITABLE_ARCH(entry)<< PAGE_WRITE_SHIFT) |234 ( PTE_EXECUTABLE_ARCH(entry)<< PAGE_EXEC_SHIFT) |235 ( (entry->type >= PTE_TYPE_SR_GLOBAL)<< PAGE_GLOBAL_SHIFT));186 (entry->user << PAGE_USER_SHIFT) | 187 (entry->readable << PAGE_READ_SHIFT) | 188 (entry->writable << PAGE_WRITE_SHIFT) | 189 (entry->executable << PAGE_EXEC_SHIFT) | 190 (entry->global << PAGE_GLOBAL_SHIFT)); 236 191 } 237 192 … … 241 196 242 197 entry->valid = !(flags & PAGE_NOT_PRESENT); 243 244 if ((flags & PAGE_WRITE) != 0) { 245 if ((flags & PAGE_EXEC) != 0) 246 entry->type = PTE_TYPE_SRWXURWX; 247 else 248 entry->type = PTE_TYPE_SRWURW; 249 } else { 250 if ((flags & PAGE_EXEC) != 0) 251 entry->type = PTE_TYPE_SRXURX; 252 else 253 entry->type = PTE_TYPE_SRUR; 254 } 198 entry->readable = (flags & PAGE_READ) != 0; 199 entry->writable = (flags & PAGE_WRITE) != 0; 200 entry->executable = (flags & PAGE_EXEC) != 0; 201 entry->user = (flags & PAGE_USER) != 0; 202 entry->global = (flags & PAGE_GLOBAL) != 0; 203 entry->accessed = 1; 204 entry->dirty = 1; 255 205 } 256 206 … … 264 214 extern void page_arch_init(void); 265 215 extern void page_fault(unsigned int, istate_t *); 216 extern void write_satp(uintptr_t); 266 217 267 218 #endif /* __ASM__ */ -
kernel/arch/riscv64/src/mm/as.c
rc16479e rccc362a1 40 40 } 41 41 42 /** Install address space. 43 * 44 * Install ASID. 45 * 46 * @param as Address space structure. 47 */ 48 void as_install_arch(as_t *as) 49 { 50 // FIXME 51 } 52 42 53 /** @} 43 54 */ -
kernel/arch/riscv64/src/mm/frame.c
rc16479e rccc362a1 32 32 33 33 #include <mm/frame.h> 34 #include <arch/boot/boot.h> 34 35 #include <arch/mm/frame.h> 36 #include <arch/drivers/ucb.h> 35 37 #include <mm/as.h> 36 38 #include <config.h> … … 39 41 #include <align.h> 40 42 #include <macros.h> 41 42 43 #include <print.h> 43 44 44 size_t hardcoded_unmapped_ktext_size = 0; 45 size_t hardcoded_unmapped_kdata_size = 0; 45 uintptr_t physmem_start; 46 uintptr_t htif_frame; 47 uintptr_t pt_frame; 48 memmap_t memmap; 46 49 47 50 void physmem_print(void) … … 49 52 } 50 53 54 static void frame_common_arch_init(bool low) 55 { 56 pfn_t minconf = 57 max3(ADDR2PFN(physmem_start), htif_frame + 1, pt_frame + 1); 58 59 for (size_t i = 0; i < memmap.cnt; i++) { 60 /* To be safe, make the available zone possibly smaller */ 61 uintptr_t base = ALIGN_UP((uintptr_t) memmap.zones[i].start, 62 FRAME_SIZE); 63 size_t size = ALIGN_DOWN(memmap.zones[i].size - 64 (base - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE); 65 66 if (!frame_adjust_zone_bounds(low, &base, &size)) 67 return; 68 69 pfn_t pfn = ADDR2PFN(base); 70 size_t count = SIZE2FRAMES(size); 71 pfn_t conf; 72 73 if (low) { 74 if ((minconf < pfn) || (minconf >= pfn + count)) 75 conf = pfn; 76 else 77 conf = minconf; 78 79 zone_create(pfn, count, conf, 80 ZONE_AVAILABLE | ZONE_LOWMEM); 81 } else { 82 conf = zone_external_conf_alloc(count); 83 if (conf != 0) 84 zone_create(pfn, count, conf, 85 ZONE_AVAILABLE | ZONE_HIGHMEM); 86 } 87 } 88 } 51 89 52 90 void frame_low_arch_init(void) 53 91 { 92 frame_common_arch_init(true); 93 94 frame_mark_unavailable(htif_frame, 1); 95 frame_mark_unavailable(pt_frame, 1); 54 96 } 55 97 56 98 void frame_high_arch_init(void) 57 99 { 100 frame_common_arch_init(false); 58 101 } 59 102 -
kernel/arch/riscv64/src/mm/km.c
rc16479e rccc362a1 32 32 33 33 #include <arch/mm/km.h> 34 #include <mm/km.h> 34 35 #include <stdbool.h> 35 36 #include <typedefs.h> 37 #include <macros.h> 36 38 37 39 void km_identity_arch_init(void) 38 40 { 41 config.identity_base = KM_RISCV64_IDENTITY_START; 42 config.identity_size = KM_RISCV64_IDENTITY_SIZE; 39 43 } 40 44 41 45 void km_non_identity_arch_init(void) 42 46 { 47 km_non_identity_span_add(KM_RISCV64_NON_IDENTITY_START, 48 KM_RISCV64_NON_IDENTITY_SIZE); 43 49 } 44 50 45 51 bool km_is_non_identity_arch(uintptr_t addr) 46 52 { 47 return false; 53 return iswithin(KM_RISCV64_NON_IDENTITY_START, 54 KM_RISCV64_NON_IDENTITY_SIZE, addr, 1); 48 55 } 49 56 -
kernel/arch/riscv64/src/mm/page.c
rc16479e rccc362a1 48 48 #include <interrupt.h> 49 49 50 #define SATP_PFN_MASK UINT64_C(0x00000fffffffffff) 51 52 #define SATP_MODE_MASK UINT64_C(0xf000000000000000) 53 #define SATP_MODE_BARE UINT64_C(0x0000000000000000) 54 #define SATP_MODE_SV39 UINT64_C(0x8000000000000000) 55 #define SATP_MODE_SV48 UINT64_C(0x9000000000000000) 56 50 57 void page_arch_init(void) 51 58 { 52 if (config.cpu_active == 1) 59 if (config.cpu_active == 1) { 53 60 page_mapping_operations = &pt_mapping_operations; 61 62 page_table_lock(AS_KERNEL, true); 63 64 /* 65 * PA2KA(identity) mapping for all low-memory frames. 66 */ 67 for (uintptr_t cur = 0; 68 cur < min(config.identity_size, config.physmem_end); 69 cur += FRAME_SIZE) 70 page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, 71 PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_EXEC | PAGE_WRITE | PAGE_READ); 72 73 page_table_unlock(AS_KERNEL, true); 74 75 // FIXME: register page fault extension handler 76 77 write_satp((uintptr_t) AS_KERNEL->genarch.page_table); 78 79 /* The boot page table is no longer needed. */ 80 // FIXME: frame_mark_available(pt_frame, 1); 81 } 54 82 } 55 83 … … 58 86 } 59 87 88 void write_satp(uintptr_t ptl0) 89 { 90 uint64_t satp = ((ptl0 >> FRAME_WIDTH) & SATP_PFN_MASK) | 91 SATP_MODE_SV48; 92 93 asm volatile ( 94 "csrw sptbr, %[satp]\n" 95 :: [satp] "r" (satp) 96 ); 97 } 98 60 99 /** @} 61 100 */ -
kernel/arch/riscv64/src/riscv64.c
rc16479e rccc362a1 49 49 #include <console/console.h> 50 50 #include <mem.h> 51 #include <str.h> 51 52 52 53 char memcpy_from_uspace_failover_address; 53 54 char memcpy_to_uspace_failover_address; 54 55 56 static void riscv64_post_mm_init(void); 57 55 58 arch_ops_t riscv64_ops = { 59 .post_mm_init = riscv64_post_mm_init 56 60 }; 57 61 58 62 arch_ops_t *arch_ops = &riscv64_ops; 63 64 void riscv64_pre_main(bootinfo_t *bootinfo) 65 { 66 physmem_start = bootinfo->physmem_start; 67 htif_frame = bootinfo->htif_frame; 68 pt_frame = bootinfo->pt_frame; 69 70 htif_init(bootinfo->ucbinfo.tohost, bootinfo->ucbinfo.fromhost); 71 72 /* Copy tasks map. */ 73 init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, 74 CONFIG_INIT_TASKS); 75 76 for (size_t i = 0; i < init.cnt; i++) { 77 init.tasks[i].paddr = KA2PA(bootinfo->taskmap.tasks[i].addr); 78 init.tasks[i].size = bootinfo->taskmap.tasks[i].size; 79 str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN, 80 bootinfo->taskmap.tasks[i].name); 81 } 82 83 /* Copy physical memory map. */ 84 memmap.total = bootinfo->memmap.total; 85 memmap.cnt = min(bootinfo->memmap.cnt, MEMMAP_MAX_RECORDS); 86 for (size_t i = 0; i < memmap.cnt; i++) { 87 memmap.zones[i].start = bootinfo->memmap.zones[i].start; 88 memmap.zones[i].size = bootinfo->memmap.zones[i].size; 89 } 90 } 91 92 void riscv64_post_mm_init(void) 93 { 94 outdev_t *htifout = htifout_init(); 95 if (htifout) 96 stdout_wire(htifout); 97 } 59 98 60 99 void calibrate_delay_loop(void) … … 90 129 } 91 130 92 int context_save_arch(context_t *ctx)93 {94 return 1;95 }96 97 void context_restore_arch(context_t *ctx)98 {99 while (true);100 }101 102 131 void fpu_init(void) 103 132 { … … 122 151 } 123 152 124 void early_putchar(wchar_t ch)125 {126 }127 128 153 /** @} 129 154 */
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