Changeset cf538e7 in mainline

Timestamp:

2012-12-11T22:20:04Z (12 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

14febed9

Parents:

d704d7f

Message:

Behaviour of the TLB invalid exception is different on 4Kc than on R4000.

File:

• kernel/arch/mips32/src/mm/tlb.c (modified) (1 diff)

kernel/arch/mips32/src/mm/tlb.c

@@ -142 +142 @@
         index.value = cp0_index_read();
 
+#if defined(PROCESSOR_4Kc)
+        /*
+         * This can happen on a 4Kc when Status.EXL is 1 and there is a TLB miss.
+         * EXL is 1 when interrupts are disabled. The combination of a TLB miss
+         * and disabled interrupts is possible in copy_to/from_uspace().
+         */
+        if (index.p) {
+                tlb_refill(istate);
+                return;
+        }
+#endif
+
         ASSERT(!index.p);