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  • uspace/drv/audio/hdaudio/hdactl.c

    ra64970e1 rcf78637  
    11/*
    2  * Copyright (c) 2025 Jiri Svoboda
     2 * Copyright (c) 2014 Jiri Svoboda
    33 * All rights reserved.
    44 *
     
    628628}
    629629
    630 void hda_ctl_quiesce(hda_ctl_t *ctl)
    631 {
    632         uint32_t gctl;
    633 
    634         ddf_msg(LVL_DEBUG, "hda_ctl_quiesce(): Resetting controller.");
    635         gctl = hda_reg32_read(&ctl->hda->regs->gctl);
    636         hda_reg32_write(&ctl->hda->regs->gctl,
    637             gctl & ~BIT_V(uint32_t, gctl_crst));
    638 }
    639 
    640630errno_t hda_cmd(hda_t *hda, uint32_t verb, uint32_t *resp)
    641631{
     
    680670}
    681671
    682 static void hda_ctl_check_fifo_error(hda_ctl_t *ctl)
    683 {
    684         int i;
    685         uint8_t sts;
    686 
    687         /*
    688          * XXX Ideally the interrupt handler would tell us which stream
    689          * has the error.
    690          */
    691 
    692         for (i = 0; i < 30; i++) {
    693                 sts = hda_reg8_read(&ctl->hda->regs->sdesc[i].sts);
    694                 if ((sts & BIT_V(uint8_t, sdsts_fifoe)) != 0 && (sts & 0x80) == 0) {
    695                         ddf_msg(LVL_WARN, "sts[%d] = 0x%hhx\n", i, sts);
    696                         hda_reg8_write(&ctl->hda->regs->sdesc[i].sts,
    697                             BIT_V(uint8_t, sdsts_fifoe));
    698                 }
    699         }
    700 }
    701 
    702672void hda_ctl_interrupt(hda_ctl_t *ctl)
    703673{
    704         ddf_msg(LVL_DEBUG, "hda_ctl_interrupt");
    705         hda_ctl_check_fifo_error(ctl);
    706674        hda_ctl_process_rirb(ctl);
    707675}
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