Changeset d0780b4c in mainline for arch/ia32/src/smp/apic.c

Timestamp:

2006-01-29T19:55:08Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

df09142f

Parents:

457d18a

Message:

ia32 SMP updates.
Update info about supported version of Bochs (bump the counter to 2.2.6).
Add Task Priority Register type and initialize this register to a known state.

File:

• arch/ia32/src/smp/apic.c (modified) (4 diffs)

arch/ia32/src/smp/apic.c

@@ -45 +45 @@
  * Advanced Programmable Interrupt Controller for SMP systems.
  * Tested on:
- *      Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs
+ *      Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
  *      Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
  *      VMware Workstation 5.5 with 2 CPUs
@@ -309 +309 @@
         lvt_error_t error;
         lvt_lint_t lint;
+        tpr_t tpr;
         svr_t svr;
         icr_t icr;
@@ -331 +332 @@
         lint.masked = true;
         l_apic[LVT_LINT1] = lint.value;
+
+        /* Task Priority Register initialization. */
+        tpr.value = l_apic[TPR];
+        tpr.pri_sc = 0;
+        tpr.pri = 0;
+        l_apic[TPR] = tpr.value;
         
         /* Spurious-Interrupt Vector Register initialization. */
@@ -336 +343 @@
         svr.vector = VECTOR_APIC_SPUR;
         svr.lapic_enabled = true;
+        svr.focus_checking = true;
         l_apic[SVR] = svr.value;
-
-        l_apic[TPR] &= TPRClear;
 
         if (CPU->arch.family >= 6)