Changeset d085df10 in mainline


Ignore:
Timestamp:
2012-09-23T16:19:26Z (12 years ago)
Author:
Maurizio Lombardi <m.lombardi85@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
21aab25
Parents:
47d2ca9 (diff), 40ad375 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

merge changes from the beagleboard-xm branch

Files:
13 edited

Legend:

Unmodified
Added
Removed

  • HelenOS.config

    r47d2ca9 rd085df10  
    615615@ "efi" GRUB for UEFI
    616616! [PLATFORM=ia32|PLATFORM=amd64] GRUB_ARCH (choice)
     617
     618% uImage OS type
     619@ "2" NetBSD stage 2 boot loader
     620! [PLATFORM=arm32&MACHINE=beagleboardxm] UIMAGE_OS (choice)
     621
     622% uImage OS type
     623@ "5" Linux kernel
     624! [PLATFORM=arm32&MACHINE!=beagleboardxm] UIMAGE_OS (choice)

  • boot/Makefile.uboot

    r47d2ca9 rd085df10  
    4040
    4141$(POST_OUTPUT): $(BIN_OUTPUT)
    42         $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr $(LADDR) -saddr $(SADDR) $< $@
     42        $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr $(LADDR) -saddr $(SADDR) -ostype $(UIMAGE_OS) $< $@
    4343
    4444clean:

  • boot/arch/arm32/Makefile.inc

    r47d2ca9 rd085df10  
    4949BITS = 32
    5050ENDIANESS = LE
    51 EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR))
     51EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
    5252
    5353ifeq ($(MACHINE), gta02)

  • defaults/arm32/gta02/Makefile.config

    r47d2ca9 rd085df10  
    33
    44# RAM disk format
    5 RDFMT = tmpfs
     5RDFMT = fat

  • kernel/arch/arm32/Makefile.inc

    r47d2ca9 rd085df10  
    3333ATSIGN = %
    3434
    35 GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR))
     35GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
    3636
    3737BITS = 32

  • kernel/arch/arm32/include/asm.h

    r47d2ca9 rd085df10  
    4646 *
    4747 * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi).
     48 * ARM920T has custom coprocessor action to do the same. See ARM920T Technical
     49 * Reference Manual ch 4.9 p. 4-23 (103 in the PDF)
    4850 */
    4951NO_TRACE static inline void cpu_sleep(void)
    … …  
    5153#ifdef PROCESSOR_armv7_a
    5254        asm volatile ( "wfe" :: );
     55#elif defined(MACHINE_gta02)
     56        asm volatile ( "mcr p15,0,R0,c7,c0,4" :: );
    5357#endif
    5458}

  • kernel/arch/arm32/include/barrier.h

    r47d2ca9 rd085df10  
    4747#define write_barrier()   asm volatile ("" ::: "memory")
    4848
    49 #define smc_coherence(a)
    50 #define smc_coherence_block(a, l)
     49/*
     50 * There are multiple ways ICache can be implemented on ARM machines. Namely
     51 * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference
     52 * Manual B3.11.2 (p. 1383).  However, CortexA8 Manual states: "For maximum
     53 * compatibility across processors, ARM recommends that operating systems target
     54 * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches,
     55 * and do not assume the presence of the IVIPT extension. Software that relies
     56 * on the IVIPT extension might fail in an unpredictable way on an ARMv7
     57 * implementation that does not include the IVIPT extension." (7.2.6 p. 245).
     58 * Only PIPT invalidates cache for all VA aliases if one block is invalidated.
     59 *
     60 * @note: Supporting ASID and VMID tagged VIVT may need to add ICache
     61 * maintenance to other places than just smc.
     62 */
     63
     64/* Available on both all supported arms,
     65 * invalidates entire ICache so the written value does not matter. */
     66#define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
     67#define smc_coherence_block(a, l) smc_coherence(a)
     68
    5169
    5270#endif

  • kernel/arch/arm32/include/regutils.h

    r47d2ca9 rd085df10  
    4141#define STATUS_REG_MODE_MASK         0x1f
    4242
    43 #define CP15_R1_MMU_ENABLE_BIT       (1 << 0)
    44 #define CP15_R1_ALIGNMENT_ENABLE_BIT (1 << 1)
    45 #define CP15_R1_CACHE_ENABLE_BIT     (1 << 2)
    46 #define CP15_R1_BRANCH_PREDICT_BIT   (1 << 11)
    47 #define CP15_R1_INST_CACHE_BIT       (1 << 12)
    48 #define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
    49 #define CP15_R1_ROUND_ROBIN_BIT      (1 << 14)
    50 #define CP15_R1_HA_ENABLE_BIT        (1 << 17)
    51 #define CP15_R1_WXN_BIT              (1 << 19) /* Only if virt. supported */
    52 #define CP15_R1_UWXN_BIT             (1 << 20) /* Only if virt. supported */
    53 #define CP15_R1_FI_BIT               (1 << 21)
    54 #define CP15_R1_VE_BIT               (1 << 24)
    55 #define CP15_R1_EE_BIT               (1 << 25)
    56 #define CP15_R1_NMFI_BIT             (1 << 27)
    57 #define CP15_R1_TRE_BIT              (1 << 28)
    58 #define CP15_R1_AFE_BIT              (1 << 29)
     43/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
     44 * Manual ARMv7-A and ARMv7-R edition, page 1687 */
     45#define CP15_R1_MMU_EN            (1 << 0)
     46#define CP15_R1_ALIGN_CHECK_EN    (1 << 1)  /* Allow alignemnt check */
     47#define CP15_R1_CACHE_EN          (1 << 2)
     48#define CP15_R1_CP15_BARRIER_EN   (1 << 5)
     49#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only big endian switch */
     50#define CP15_R1_SWAP_EN           (1 << 10)
     51#define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
     52#define CP15_R1_INST_CACHE_EN     (1 << 12)
     53#define CP15_R1_HIGH_VECTORS_EN   (1 << 13)
     54#define CP15_R1_ROUND_ROBIN_EN    (1 << 14)
     55#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17)
     56#define CP15_R1_WRITE_XN_EN       (1 << 19) /* Only if virt. supported */
     57#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */
     58#define CP15_R1_FAST_IRQ_EN       (1 << 21) /* Disbale impl.specific features */
     59#define CP15_R1_UNALIGNED_EN      (1 << 22) /* Must be 1 on armv7 */
     60#define CP15_R1_IRQ_VECTORS_EN    (1 << 24)
     61#define CP15_R1_BIG_ENDIAN_EXC    (1 << 25)
     62#define CP15_R1_NMFI_EN           (1 << 27)
     63#define CP15_R1_TEX_REMAP_EN      (1 << 28)
     64#define CP15_R1_ACCESS_FLAG_EN    (1 << 29)
     65#define CP15_R1_THUMB_EXC_EN      (1 << 30)
    5966
    6067/* ARM Processor Operation Modes */

  • kernel/arch/arm32/src/cpu/cpu.c

    r47d2ca9 rd085df10  
    9797}
    9898
    99 /** Does nothing on ARM. */
     99/** Enables unaligned access and caching for armv6+ */
    100100void cpu_arch_init(void)
    101101{
    102 #if defined(PROCESSOR_armv7_a)
     102#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
    103103        uint32_t control_reg = 0;
    104104        asm volatile (
    … …  
    107107        );
    108108       
    109         /* Turn off tex remap */
    110         control_reg &= ~CP15_R1_TRE_BIT;
    111         /* Turn off accessed flag */
    112         control_reg &= ~(CP15_R1_AFE_BIT | CP15_R1_HA_ENABLE_BIT);
    113         /* Enable caching */
    114         control_reg |= CP15_R1_CACHE_ENABLE_BIT;
     109        /* Turn off tex remap, RAZ ignores writes prior to armv7 */
     110        control_reg &= ~CP15_R1_TEX_REMAP_EN;
     111        /* Turn off accessed flag, RAZ ignores writes prior to armv7 */
     112        control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
     113        /* Enable unaligned access, RAZ ignores writes prior to armv6
     114         * switchable on armv6, RAO ignores writes on armv7,
     115         * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
     116         * L.3.1 (p. 2456) */
     117        control_reg |= CP15_R1_UNALIGNED_EN;
     118        /* Disable alignment checks, this turns unaligned access to undefined,
     119         * unless U bit is set. */
     120        control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
     121        /* Enable caching, On arm prior to armv7 there is only one level
     122         * of caches. Data cache is coherent.
     123         * "This means that the behavior of accesses from the same observer to
     124         * different VAs, that are translated to the same PA
     125         * with the same memory attributes, is fully coherent."
     126         *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
     127         *    B3.11.1 (p. 1383)
     128         * ICache coherency is elaborate on in barrier.h.
     129         * We are safe to turn these on.
     130         */
     131        control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
    115132       
    116133        asm volatile (
    … …  
    122139
    123140/** Retrieves processor identification and stores it to #CPU.arch */
    124 void cpu_identify(void) 
     141void cpu_identify(void)
    125142{
    126143        arch_cpu_identify(&CPU->arch);

  • kernel/arch/arm32/src/exception.c

    r47d2ca9 rd085df10  
    143143       
    144144        /* switch on the high vectors bit */
    145         control_reg |= CP15_R1_HIGH_VECTORS_BIT;
     145        control_reg |= CP15_R1_HIGH_VECTORS_EN;
    146146       
    147147        asm volatile (

  • kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

    r47d2ca9 rd085df10  
    9696                ++order;
    9797        }
    98         printf("Allocating %d (2^%d) frames.\n", size, order);
    9998        /* prefer highmem as we don't care about virtual mapping. */
    10099        void *buffer = frame_alloc(order, FRAME_LOWMEM);
    101         ASSERT(buffer);
     100        if (!buffer) {
     101                printf("Failed to allocate framebuffer.\n");
     102                return;
     103        }
    102104
    103105        amdm37x_dispc_setup_fb(beagleboard.dispc, width, height, bpp,

  • kernel/arch/arm32/src/mm/page_fault.c

    r47d2ca9 rd085df10  
    4141#include <interrupt.h>
    4242#include <print.h>
     43
     44
     45/**
     46 * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.
     47 *
     48 * B3.13.3 page B3-1406 (PDF page 1406)
     49 */
     50typedef enum {
     51        DFSR_SOURCE_ALIGN = 0x0001,
     52        DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004,
     53        DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c,
     54        DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e,
     55        DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c,
     56        DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e,
     57        DFSR_SOURCE_TRANSLATION_L1 = 0x0005,
     58        DFSR_SOURCE_TRANSLATION_L2 = 0x0007,
     59        DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003,  /**< @note: This used to be alignment enc. */
     60        DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006,
     61        DFSR_SOURCE_DOMAIN_L1 = 0x0009,
     62        DFSR_SOURCE_DOMAIN_L2 = 0x000b,
     63        DFSR_SOURCE_PERMISSION_L1 = 0x000d,
     64        DFSR_SOURCE_PERMISSION_L2 = 0x000f,
     65        DFSR_SOURCE_DEBUG = 0x0002,
     66        DFSR_SOURCE_SYNC_EXTERNAL = 0x0008,
     67        DFSR_SOURCE_TLB_CONFLICT = 0x0400,
     68        DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */
     69        DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */
     70        DFSR_SOURCE_SYNC_PARITY = 0x0409,
     71        DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406,
     72        DFSR_SOURCE_ASYNC_PARITY = 0x0408,
     73        DFSR_SOURCE_MASK = 0x0000040f,
     74} dfsr_source_t;
     75
     76static inline const char * dfsr_source_to_str(dfsr_source_t source)
     77{
     78        switch (source) {
     79        case DFSR_SOURCE_TRANSLATION_L1:
     80                return "Translation fault L1";
     81        case DFSR_SOURCE_TRANSLATION_L2:
     82                return "Translation fault L2";
     83        case DFSR_SOURCE_PERMISSION_L1:
     84                return "Permission fault L1";
     85        case DFSR_SOURCE_PERMISSION_L2:
     86                return "Permission fault L2";
     87        case DFSR_SOURCE_ALIGN:
     88                return "Alignment fault";
     89        case DFSR_SOURCE_CACHE_MAINTENANCE:
     90                return "Instruction cache maintenance fault";
     91        case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
     92                return "Synchronous external abort on translation table walk level 1";
     93        case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
     94                return "Synchronous external abort on translation table walk level 2";
     95        case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
     96                return "Synchronous parity error on translation table walk level 1";
     97        case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
     98                return "Synchronous parity error on translation table walk level 2";
     99        case DFSR_SOURCE_ACCESS_FLAG_L1:
     100                return "Access flag fault L1";
     101        case DFSR_SOURCE_ACCESS_FLAG_L2:
     102                return "Access flag fault L2";
     103        case DFSR_SOURCE_DOMAIN_L1:
     104                return "Domain fault L1";
     105        case DFSR_SOURCE_DOMAIN_L2:
     106                return "Domain flault L2";
     107        case DFSR_SOURCE_DEBUG:
     108                return "Debug event";
     109        case DFSR_SOURCE_SYNC_EXTERNAL:
     110                return "Synchronous external abort";
     111        case DFSR_SOURCE_TLB_CONFLICT:
     112                return "TLB conflict abort";
     113        case DFSR_SOURCE_LOCKDOWN:
     114                return "Lockdown (Implementation defined)";
     115        case DFSR_SOURCE_COPROCESSOR:
     116                return "Coprocessor abort (Implementation defined)";
     117        case DFSR_SOURCE_SYNC_PARITY:
     118                return "Synchronous parity error on memory access";
     119        case DFSR_SOURCE_ASYNC_EXTERNAL:
     120                return "Asynchronous external abort";
     121        case DFSR_SOURCE_ASYNC_PARITY:
     122                return "Asynchronous parity error on memory access";
     123        case DFSR_SOURCE_MASK:
     124                break;
     125        }
     126        return "Unknown data abort";
     127}
     128
    43129
    44130/** Returns value stored in comnbined/data fault status register.
    … …  
    158244void data_abort(unsigned int exc_no, istate_t *istate)
    159245{
    160         uintptr_t badvaddr = read_data_fault_address_register();
     246        const uintptr_t badvaddr = read_data_fault_address_register();
     247        const fault_status_t fsr = read_data_fault_status_register();
     248        const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
     249
     250        switch (source) {
     251        case DFSR_SOURCE_TRANSLATION_L1:
     252        case DFSR_SOURCE_TRANSLATION_L2:
     253        case DFSR_SOURCE_PERMISSION_L1:
     254        case DFSR_SOURCE_PERMISSION_L2:
     255                /* Page fault is handled further down */
     256                break;
     257        case DFSR_SOURCE_ALIGN:
     258        case DFSR_SOURCE_CACHE_MAINTENANCE:
     259        case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
     260        case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
     261        case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
     262        case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
     263        case DFSR_SOURCE_ACCESS_FLAG_L1:
     264        case DFSR_SOURCE_ACCESS_FLAG_L2:
     265        case DFSR_SOURCE_DOMAIN_L1:
     266        case DFSR_SOURCE_DOMAIN_L2:
     267        case DFSR_SOURCE_DEBUG:
     268        case DFSR_SOURCE_SYNC_EXTERNAL:
     269        case DFSR_SOURCE_TLB_CONFLICT:
     270        case DFSR_SOURCE_LOCKDOWN:
     271        case DFSR_SOURCE_COPROCESSOR:
     272        case DFSR_SOURCE_SYNC_PARITY:
     273        case DFSR_SOURCE_ASYNC_EXTERNAL:
     274        case DFSR_SOURCE_ASYNC_PARITY:
     275        case DFSR_SOURCE_MASK:
     276                /* Weird abort stuff */
     277                fault_if_from_uspace(istate, "Unhandled abort %s at address: "
     278                    "%#x.", dfsr_source_to_str(source), badvaddr);
     279                panic("Unhandled abort %s at address: %#x.",
     280                    dfsr_source_to_str(source), badvaddr);
     281        }
    161282
    162283#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
    163         fault_status_t fsr = read_data_fault_status_register();
    164284        const pf_access_t access =
    165285            fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
    … …  
    169289#error "Unsupported architecture"
    170290#endif
    171         int ret = as_page_fault(badvaddr, access, istate);
     291        const int ret = as_page_fault(badvaddr, access, istate);
    172292
    173293        if (ret == AS_PF_FAULT) {

  • tools/mkuimage.py

    r47d2ca9 rd085df10  
    6060        load_addr = 0
    6161        start_addr = 0
     62        os_type = 5 #Linux is the default
    6263
    6364        while len(args) >= 2 and args[0][0] == '-':
    … …  
    7172                elif opt == 'saddr':
    7273                        start_addr = (int)(optarg, 0)
     74                elif opt == 'ostype':
     75                        os_type = (int)(optarg, 0)
    7376                else:
    7477                        print(base_name + ": Unrecognized option.")
    … …  
    8588
    8689        try:
    87                 mkuimage(inf_name, outf_name, image_name, load_addr, start_addr)
     90                mkuimage(inf_name, outf_name, image_name, load_addr, start_addr, os_type)
    8891        except:
    8992                os.remove(outf_name)
    9093                raise
    9194
    92 def mkuimage(inf_name, outf_name, image_name, load_addr, start_addr):
     95def mkuimage(inf_name, outf_name, image_name, load_addr, start_addr, os_type):
    9396        inf = open(inf_name, 'rb')
    9497        outf = open(outf_name, 'wb')
    … …  
    120123        header.start_addr = start_addr  # Address of entry point
    121124        header.data_crc = data_crc
    122         header.os = 2                   # NetBSD
     125        header.os = os_type
    123126        header.arch = 2                 # ARM
    124127        header.img_type = 2             # Kernel
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