Changes in kernel/arch/amd64/src/pm.c [650cd22:d242cb6] in mainline
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kernel/arch/amd64/src/pm.c
r650cd22 rd242cb6 49 49 50 50 descriptor_t gdt[GDT_ITEMS] = { 51 [NULL_DES] = { 52 0 53 }, 54 [KTEXT_DES] = { 55 .limit_0_15 = 0xffffU, 56 .limit_16_19 = 0xfU, 57 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 58 .longmode = 1, 59 .granularity = 1 60 }, 61 [KDATA_DES] = { 62 .limit_0_15 = 0xffffU, 63 .limit_16_19 = 0xfU, 64 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 65 .granularity = 1 66 }, 67 [UDATA_DES] = { 68 .limit_0_15 = 0xffffU, 69 .limit_16_19 = 0xfU, 70 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 71 .special = 1, 72 .granularity = 1 73 }, 74 [UTEXT_DES] = { 75 .limit_0_15 = 0xffffU, 76 .limit_16_19 = 0xfU, 77 .access = AR_PRESENT | AR_CODE | DPL_USER, 78 .longmode = 1, 79 .granularity = 1 80 }, 81 [KTEXT32_DES] = { 82 .limit_0_15 = 0xffffU, 83 .limit_16_19 = 0xfU, 84 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 85 .special = 1, 86 .granularity = 1 87 }, 88 /* 89 * TSS descriptor - set up will be completed later, 90 * on AMD64 it is 64-bit - 2 items in the table 91 */ 92 [TSS_DES] = { 93 0 94 }, 95 [TSS_DES + 1] = { 96 0 97 }, 51 /* NULL descriptor */ 52 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 53 /* KTEXT descriptor */ 54 { .limit_0_15 = 0xffffU, 55 .base_0_15 = 0, 56 .base_16_23 = 0, 57 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 58 .limit_16_19 = 0x0fU, 59 .available = 0, 60 .longmode = 1, 61 .special = 0, 62 .granularity = 1, 63 .base_24_31 = 0 }, 64 /* KDATA descriptor */ 65 { .limit_0_15 = 0xffffU, 66 .base_0_15 = 0, 67 .base_16_23 = 0, 68 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 69 .limit_16_19 = 0x0fU, 70 .available = 0, 71 .longmode = 0, 72 .special = 0, 73 .granularity = 1, 74 .base_24_31 = 0 }, 75 /* UDATA descriptor */ 76 { .limit_0_15 = 0xffffU, 77 .base_0_15 = 0, 78 .base_16_23 = 0, 79 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 80 .limit_16_19 = 0x0fU, 81 .available = 0, 82 .longmode = 0, 83 .special = 1, 84 .granularity = 1, 85 .base_24_31 = 0 }, 86 /* UTEXT descriptor */ 87 { .limit_0_15 = 0xffffU, 88 .base_0_15 = 0, 89 .base_16_23 = 0, 90 .access = AR_PRESENT | AR_CODE | DPL_USER, 91 .limit_16_19 = 0x0fU, 92 .available = 0, 93 .longmode = 1, 94 .special = 0, 95 .granularity = 1, 96 .base_24_31 = 0 }, 97 /* KTEXT 32-bit protected, for protected mode before long mode */ 98 { .limit_0_15 = 0xffffU, 99 .base_0_15 = 0, 100 .base_16_23 = 0, 101 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 102 .limit_16_19 = 0x0fU, 103 .available = 0, 104 .longmode = 0, 105 .special = 1, 106 .granularity = 1, 107 .base_24_31 = 0 }, 108 /* TSS descriptor - set up will be completed later, 109 * on AMD64 it is 64-bit - 2 items in table */ 110 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 111 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 98 112 /* VESA Init descriptor */ 99 113 #ifdef CONFIG_FB 100 [VESA_INIT_CODE_DES] = { 101 .limit_0_15 = 0xffff, 102 .limit_16_19 = 0xf, 103 .base_16_23 = VESA_INIT_SEGMENT >> 12, 104 .access = AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL 105 }, 106 [VESA_INIT_DATA_DES] = { 107 .limit_0_15 = 0xffff, 108 .limit_16_19 = 0xf, 109 .base_16_23 = VESA_INIT_SEGMENT >> 12, 110 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL 111 } 114 { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }, 115 { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 } 112 116 #endif 113 117 }; … … 115 119 idescriptor_t idt[IDT_ITEMS]; 116 120 117 ptr_16_64_t gdtr = { 118 .limit = sizeof(gdt), 119 .base = (uint64_t) gdt 120 }; 121 ptr_16_64_t idtr = { 122 .limit = sizeof(idt), 123 .base = (uint64_t) idt 124 }; 121 ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base = (uint64_t) gdt }; 122 ptr_16_64_t idtr = {.limit = sizeof(idt), .base = (uint64_t) idt }; 125 123 126 124 static tss_t tss;
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