Changes in kernel/arch/ia32/src/pm.c [0f17bff:d242cb6] in mainline

File:

• kernel/arch/ia32/src/pm.c (modified) (7 diffs)

kernel/arch/ia32/src/pm.c

@@ -41 +41 @@
 #include <panic.h>
 #include <arch/mm/page.h>
-#include <mm/km.h>
-#include <mm/frame.h>
 #include <mm/slab.h>
 #include <memstr.h>
 #include <arch/boot/boot.h>
 #include <interrupt.h>
-#include <arch/cpu.h>
 
 /*
@@ -54 +51 @@
 
 /*
- * We don't have much use for segmentation so we set up flat mode.
- * In this mode, we use, for each privilege level, two segments spanning the
+ * We have no use for segmentation so we set up flat mode. In this
+ * mode, we use, for each privilege level, two segments spanning the
  * whole memory. One is for code and one is for data.
  *
- * One special segment apart of that is for the GS register which holds
- * a pointer to the VREG page in its base.
+ * One is for GS register which holds pointer to the TLS thread
+ * structure in it's base.
  */
 descriptor_t gdt[GDT_ITEMS] = {
-        [NULL_DES] = {
-                0
-        },
-        [KTEXT_DES] = {
-                .limit_0_15 = 0xffff,
-                .limit_16_19 = 0xf,
-                .access = AR_PRESENT | AR_CODE | DPL_KERNEL,
-                .special = 1,
-                .granularity = 1
-        },
-        [KDATA_DES] = {
-                .limit_0_15 = 0xffff,
-                .limit_16_19 = 0xf,
-                .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
-                .special = 1,
-                .granularity = 1
-        },
-        [UTEXT_DES] = {
-                .limit_0_15 = 0xffff,
-                .limit_16_19 = 0xf,
-                .access = AR_PRESENT | AR_CODE | DPL_USER,
-                .special = 1,
-                .granularity = 1
-        },
-        [UDATA_DES] = {
-                .limit_0_15 = 0xffff,
-                .limit_16_19 = 0xf,
-                .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
-                .special = 1,
-                .granularity = 1
-        },
-        [TSS_DES] = {           /* set up will be completed later */
-                0,
-        },
-        [VREG_DES] = {          /* will be reinitialized later */
-                .limit_0_15 = 0xffff,
-                .limit_16_19 = 0xf,
-                .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
-                .special = 1,
-                .granularity = 1
-        },
+        /* NULL descriptor */
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+        /* KTEXT descriptor */
+        { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
+        /* KDATA descriptor */
+        { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
+        /* UTEXT descriptor */
+        { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
+        /* UDATA descriptor */
+        { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
+        /* TSS descriptor - set up will be completed later */
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+        /* TLS descriptor */
+        { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
         /* VESA Init descriptor */
 #ifdef CONFIG_FB
-        [VESA_INIT_CODE_DES] = {
-                .limit_0_15 = 0xffff,
-                .limit_16_19 = 0xf,
-                .base_16_23 = VESA_INIT_SEGMENT >> 12,
-                .access = AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL
-        },
-        [VESA_INIT_DATA_DES] = {
-                .limit_0_15 = 0xffff,
-                .limit_16_19 = 0xf,
-                .base_16_23 = VESA_INIT_SEGMENT >> 12,
-                .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL
-        }
+        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 },
+        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
 #endif
 };
@@ -122 +82 @@
 static idescriptor_t idt[IDT_ITEMS];
 
-static tss_t tss0;
+static tss_t tss;
 
 tss_t *tss_p = NULL;
@@ -135 +95 @@
 {
         d->base_0_15 = base & 0xffff;
-        d->base_16_23 = (base >> 16) & 0xff;
-        d->base_24_31 = (base >> 24) & 0xff;
+        d->base_16_23 = ((base) >> 16) & 0xff;
+        d->base_24_31 = ((base) >> 24) & 0xff;
 }
 
@@ -257 +217 @@
 }
 
+/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
+static void clean_IOPL_NT_flags(void)
+{
+        asm volatile (
+                "pushfl\n"
+                "pop %%eax\n"
+                "and $0xffff8fff, %%eax\n"
+                "push %%eax\n"
+                "popfl\n"
+                ::: "eax"
+        );
+}
+
+/* Clean AM(18) flag in CR0 register */
+static void clean_AM_flag(void)
+{
+        asm volatile (
+                "mov %%cr0, %%eax\n"
+                "and $0xfffbffff, %%eax\n"
+                "mov %%eax, %%cr0\n"
+                ::: "eax"
+        );
+}
+
 void pm_init(void)
 {
@@ -281 +265 @@
                  * the heap hasn't been initialized so far.
                  */
-                tss_p = &tss0;
-        } else {
+                tss_p = &tss;
+        }
+        else {
                 tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
                 if (!tss_p)
@@ -303 +288 @@
         tr_load(GDT_SELECTOR(TSS_DES));
         
-        /* Disable I/O on nonprivileged levels and clear NT flag. */
-        write_eflags(read_eflags() & ~(EFLAGS_IOPL | EFLAGS_NT));
-
-        /* Disable alignment check */
-        write_cr0(read_cr0() & ~CR0_AM);
+        clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
+        clean_AM_flag();          /* Disable alignment check */
+}
+
+void set_tls_desc(uintptr_t tls)
+{
+        ptr_16_32_t cpugdtr;
+        descriptor_t *gdt_p;
+
+        gdtr_store(&cpugdtr);
+        gdt_p = (descriptor_t *) cpugdtr.base;
+        gdt_setbase(&gdt_p[TLS_DES], tls);
+        /* Reload gdt register to update GS in CPU */
+        gdtr_load(&cpugdtr);
 }