Changes in kernel/arch/ia32/src/pm.c [d6f9fff:d242cb6] in mainline

File:

• kernel/arch/ia32/src/pm.c (modified) (7 diffs)

kernel/arch/ia32/src/pm.c

@@ -41 +41 @@
 #include <panic.h>
 #include <arch/mm/page.h>
-#include <mm/km.h>
-#include <mm/frame.h>
 #include <mm/slab.h>
 #include <memstr.h>
@@ -53 +51 @@
 
 /*
- * We don't have much use for segmentation so we set up flat mode.
- * In this mode, we use, for each privilege level, two segments spanning the
+ * We have no use for segmentation so we set up flat mode. In this
+ * mode, we use, for each privilege level, two segments spanning the
  * whole memory. One is for code and one is for data.
  *
- * One special segment apart of that is for the GS register which holds
- * a pointer to the VREG page in its base.
+ * One is for GS register which holds pointer to the TLS thread
+ * structure in it's base.
  */
 descriptor_t gdt[GDT_ITEMS] = {
@@ -73 +71 @@
         /* TSS descriptor - set up will be completed later */
         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-        /* VREG descriptor - segment used for virtual registers, will be reinitialized later */
-        { 0xffff, 0 , 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
+        /* TLS descriptor */
+        { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
         /* VESA Init descriptor */
 #ifdef CONFIG_FB
@@ -84 +82 @@
 static idescriptor_t idt[IDT_ITEMS];
 
-static tss_t tss0;
+static tss_t tss;
 
 tss_t *tss_p = NULL;
@@ -97 +95 @@
 {
         d->base_0_15 = base & 0xffff;
-        d->base_16_23 = (base >> 16) & 0xff;
-        d->base_24_31 = (base >> 24) & 0xff;
+        d->base_16_23 = ((base) >> 16) & 0xff;
+        d->base_24_31 = ((base) >> 24) & 0xff;
 }
 
@@ -267 +265 @@
                  * the heap hasn't been initialized so far.
                  */
-                tss_p = &tss0;
-        } else {
+                tss_p = &tss;
+        }
+        else {
                 tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
                 if (!tss_p)
@@ -293 +292 @@
 }
 
+void set_tls_desc(uintptr_t tls)
+{
+        ptr_16_32_t cpugdtr;
+        descriptor_t *gdt_p;
+
+        gdtr_store(&cpugdtr);
+        gdt_p = (descriptor_t *) cpugdtr.base;
+        gdt_setbase(&gdt_p[TLS_DES], tls);
+        /* Reload gdt register to update GS in CPU */
+        gdtr_load(&cpugdtr);
+}
+
 /** @}
  */