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  • kernel/arch/mips32/include/barrier.h

    r7a0359b rd5087aa  
    2727 */
    2828
    29 /** @addtogroup mips32
     29/** @addtogroup mips32 
    3030 * @{
    3131 */
     
    3939 * TODO: implement true MIPS memory barriers for macros below.
    4040 */
    41 #define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
    42 #define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
     41#define CS_ENTER_BARRIER()      asm volatile ("" ::: "memory")
     42#define CS_LEAVE_BARRIER()      asm volatile ("" ::: "memory")
    4343
    44 #define memory_barrier() asm volatile ("" ::: "memory")
    45 #define read_barrier()   asm volatile ("" ::: "memory")
    46 #define write_barrier()  asm volatile ("" ::: "memory")
     44#define memory_barrier()        asm volatile ("" ::: "memory")
     45#define read_barrier()          asm volatile ("" ::: "memory")
     46#define write_barrier()         asm volatile ("" ::: "memory")
    4747
    4848#define smc_coherence(a)
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