Changeset d5610b9 in mainline for kernel/arch/arm32/src/cpu/cpu.c

Timestamp:

2015-10-03T08:37:37Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

afe5e09

Parents:

8ca6f08

Message:

Cleanup some of the cache maintenance mess on ARM

• Do not define ARMv7 cache maintenance registers for ARMv6-.
• Define missing ARMv6- registers using analoguos naming convention.
• In smc_coherence() and pt_coherence_m(), do not blindly use ARMv7 DCCVMAU but decide the proper type of cache maintenance operation in dcache_clean_mva_pou().
• Also, do not use ARMv7 ICIALLU directly, but call icache_invalidate() instead, which does the right thing.

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (1 diff)

kernel/arch/arm32/src/cpu/cpu.c

@@ -322 +322 @@
 void icache_invalidate(void)
 {
+#if defined(PROCESSOR_ARCH_armv7_a)
         ICIALLU_write(0);
+#else
+        ICIALL_write(0);
+#endif
+}
+
+#if !defined(PROCESSOR_ARCH_armv7_a)
+static bool cache_is_unified(void)
+{
+        if (MIDR_read() != CTR_read()) {
+                /* We have the CTR register */
+                return (CTR_read() & CTR_SEP_FLAG) != CTR_SEP_FLAG;
+        } else {
+                panic("Unknown cache type");
+        }
+}
+#endif
+
+void dcache_clean_mva_pou(uintptr_t mva)
+{
+#if defined(PROCESSOR_ARCH_armv7_a)
+        DCCMVAU_write(mva);
+#else
+        if (cache_is_unified())
+                CCMVA_write(mva);
+        else
+                DCCMVA_write(mva);
+#endif
 }