Changeset d68253a4 in mainline

Timestamp:

2008-06-02T12:47:33Z (17 years ago)

Author:

Jiri Svoboda <jirik.svoboda@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

0f44f04

Parents:

d2bdd245

Message:

Fix register-constraint typo in amd64 memstr.h and add two '&'s for symmetry's sake. (None were really causing trouble)

File:

• kernel/arch/amd64/include/memstr.h (modified) (3 diffs)

kernel/arch/amd64/include/memstr.h

@@ -89 +89 @@
                 "addq $1, %0\n\t"
                 "1:\n"
-                : "=a" (ret), "=%S" (d0), "=&D" (d1), "=&c" (d2)
+                : "=a" (ret), "=&S" (d0), "=&D" (d1), "=&c" (d2)
                 : "0" (0), "1" (src), "2" (dst), "3" ((unative_t)cnt)
         );
@@ -111 +111 @@
         asm volatile (
                 "rep stosw\n\t"
-                : "=&D" (d0), "=&c" (d1), "=a" (x)
+                : "=&D" (d0), "=&c" (d1), "=&a" (x)
                 : "0" (dst), "1" ((unative_t)cnt), "2" (x)
                 : "memory"
@@ -133 +133 @@
         asm volatile (
                 "rep stosb\n\t"
-                : "=&D" (d0), "=&c" (d1), "=a" (x)
+                : "=&D" (d0), "=&c" (d1), "=&a" (x)
                 : "0" (dst), "1" ((unative_t)cnt), "2" (x)
                 : "memory"