Changeset d6e5cbc in mainline


Ignore:
Timestamp:
2006-05-28T18:17:36Z (19 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
5552d60
Parents:
3bf5976
Message:

Added 'realtime' clock interface.
Added some asm macros as memory barriers.
Added drift computing for mips platform.

Files:
10 edited

Legend:

Unmodified
Added
Removed

  • arch/ia32/include/barrier.h

    r3bf5976 rd6e5cbc  
    3030#define __ia32_BARRIER_H__
    3131
    32 #include <arch/types.h>
    33 
    3432/*
    3533 * NOTE:
    … …  
    6159#               define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
    6260#       else
    63 #               define write_barrier()
     61#               define write_barrier()  __asm__ volatile( "" ::: "memory");
    6462#       endif
    6563#elif CONFIG_FENCES_P3
    … …  
    6967#               define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
    7068#       else
    71 #               define write_barrier()
     69#               define write_barrier()  __asm__ volatile( "" ::: "memory");
    7270#       endif
    7371#else
    … …  
    7775#               define write_barrier()  cpuid_serialization()
    7876#       else
    79 #               define write_barrier()
     77#               define write_barrier()  __asm__ volatile( "" ::: "memory");
    8078#       endif
    8179#endif

  • arch/mips32/include/barrier.h

    r3bf5976 rd6e5cbc  
    3636#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
    3737
    38 #define memory_barrier()
    39 #define read_barrier()
    40 #define write_barrier()
     38#define memory_barrier()        __asm__ volatile ("" ::: "memory")
     39#define read_barrier()          __asm__ volatile ("" ::: "memory")
     40#define write_barrier()         __asm__ volatile ("" ::: "memory")
    4141
    4242#endif

  • arch/mips32/include/cp0.h

    r3bf5976 rd6e5cbc  
    5050/*
    5151 * Magic value for use in msim.
    52  * On AMD Duron 800Mhz, this roughly seems like one us.
    5352 */
    54 #define cp0_compare_value               10000
     53#define cp0_compare_value               100000
    5554
    5655#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))

  • arch/mips32/src/interrupt.c

    r3bf5976 rd6e5cbc  
    7777}
    7878
     79/* TODO: This is SMP unsafe!!! */
     80static unsigned long nextcount;
     81/** Start hardware clock */
     82static void timer_start(void)
     83{
     84        nextcount = cp0_compare_value + cp0_count_read();
     85        cp0_compare_write(nextcount);
     86}
     87
    7988static void timer_exception(int n, istate_t *istate)
    8089{
    81         cp0_compare_write(cp0_count_read() + cp0_compare_value);
     90        unsigned long drift;
     91
     92        drift = cp0_count_read() - nextcount;
     93        while (drift > cp0_compare_value) {
     94                drift -= cp0_compare_value;
     95                CPU->missed_clock_ticks++;
     96        }
     97        nextcount = cp0_count_read() + cp0_compare_value - drift;
     98        cp0_compare_write(nextcount);
    8299        clock();
    83100}
    … …  
    101118        int_register(0, "swint0", swint0);
    102119        int_register(1, "swint1", swint1);
     120        timer_start();
    103121}
    104122

  • arch/mips32/src/mips32.c

    r3bf5976 rd6e5cbc  
    8181        /* Initialize dispatch table */
    8282        exception_init();
    83         interrupt_init();
    84 
    8583        arc_init();
    8684
    … …  
    9088        memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
    9189
     90        interrupt_init();
    9291        /*
    9392         * Switch to BEV normal level so that exception vectors point to the kernel.
    … …  
    10099         */
    101100        cp0_mask_all_int();
     101
    102102        /*
    103103         * Unmask hardware clock interrupt.
    104104         */
    105105        cp0_unmask_int(TIMER_IRQ);
    106 
    107         /*
    108          * Start hardware clock.
    109          */
    110         cp0_compare_write(cp0_compare_value + cp0_count_read());
    111106
    112107        console_init();

  • generic/include/time/clock.h

    r3bf5976 rd6e5cbc  
    3333
    3434extern void clock(void);
     35extern void clock_counter_init(void);
    3536
    3637#endif

  • generic/src/ipc/sysipc.c

    r3bf5976 rd6e5cbc  
    152152                        ipl_t ipl;
    153153                        as_t *as;
     154                        int rc;
    154155                       
    155156                        ipl = interrupts_disable();
    … …  
    159160                        interrupts_restore(ipl);
    160161                       
    161                         return as_area_share(AS, IPC_GET_ARG1(answer->data), IPC_GET_ARG2(*olddata),
    162                                              as, IPC_GET_ARG1(*olddata), IPC_GET_ARG3(*olddata));
     162                        rc = as_area_share(AS, IPC_GET_ARG1(answer->data), IPC_GET_ARG2(*olddata),
     163                                           as, IPC_GET_ARG1(*olddata), IPC_GET_ARG3(*olddata));
     164                        IPC_SET_RETVAL(answer->data, rc);
    163165                }
    164166        }

  • generic/src/main/main.c

    r3bf5976 rd6e5cbc  
    198198        tlb_init();
    199199        config.mm_initialized = true;
    200         arch_post_mm_init();   
     200        arch_post_mm_init();
    201201
    202202        version_print();
    … …  
    213213       
    214214        calibrate_delay_loop();
     215        clock_counter_init();
    215216        timeout_init();
    216217        scheduler_init();

  • generic/src/mm/as.c

    r3bf5976 rd6e5cbc  
    478478        mem_backend_t *src_backend;
    479479        mem_backend_data_t src_backend_data;
    480 
     480       
    481481        ipl = interrupts_disable();
    482482        mutex_lock(&src_as->lock);

  • generic/src/time/clock.c

    r3bf5976 rd6e5cbc  
    4949#include <atomic.h>
    5050#include <proc/thread.h>
     51#include <sysinfo/sysinfo.h>
     52#include <arch/barrier.h>
     53
     54/* Pointers to public variables with time */
     55struct ptime {
     56        __native seconds;
     57        __native useconds;
     58        __native useconds2;
     59};
     60struct ptime *public_time;
     61/* Variable holding fragment of second, so that we would update
     62 * seconds correctly
     63 */
     64static __native secfrag = 0;
     65
     66/** Initialize realtime clock counter
     67 *
     68 * The applications (and sometimes kernel) need to access accurate
     69 * information about realtime data. We allocate 1 page with these
     70 * data and update it periodically.
     71 *
     72 *
     73 */
     74void clock_counter_init(void)
     75{
     76        void *faddr;
     77
     78        faddr = (void *)PFN2ADDR(frame_alloc(0, FRAME_ATOMIC));
     79        if (!faddr)
     80                panic("Cannot allocate page for clock");
     81       
     82        public_time = (struct ptime *)PA2KA(faddr);
     83
     84        /* TODO: We would need some arch dependent settings here */
     85        public_time->seconds = 0;
     86        public_time->useconds = 0;
     87
     88        sysinfo_set_item_val("clock.faddr", NULL, (__native)faddr);
     89}
     90
     91
     92/** Update public counters
     93 *
     94 * Update it only on first processor
     95 * TODO: Do we really need so many write barriers?
     96 */
     97static void clock_update_counters(void)
     98{
     99        if (CPU->id == 0) {
     100                secfrag += 1000000/HZ;
     101                if (secfrag >= 1000000) {
     102                        public_time->useconds = 0;
     103                        write_barrier();
     104                        public_time->seconds++;
     105                        secfrag = 0;
     106                } else
     107                        public_time->useconds += 1000000/HZ;
     108                write_barrier();
     109                public_time->useconds2 = public_time->useconds;
     110                write_barrier();
     111        }
     112}
    51113
    52114/** Clock routine
    … …  
    70132         */
    71133        for (i = 0; i <= CPU->missed_clock_ticks; i++) {
     134                clock_update_counters();
    72135                spinlock_lock(&CPU->timeoutlock);
    73136                while ((l = CPU->timeout_active_head.next) != &CPU->timeout_active_head) {
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