Changeset d6e5cbc in mainline for arch/mips32/src/mips32.c

Timestamp:

2006-05-28T18:17:36Z (19 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5552d60

Parents:

3bf5976

Message:

Added 'realtime' clock interface.
Added some asm macros as memory barriers.
Added drift computing for mips platform.

File:

• arch/mips32/src/mips32.c (modified) (3 diffs)

arch/mips32/src/mips32.c

@@ -81 +81 @@
         /* Initialize dispatch table */
         exception_init();
-        interrupt_init();
-
         arc_init();
 
@@ -90 +88 @@
         memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
 
+        interrupt_init();
         /*
          * Switch to BEV normal level so that exception vectors point to the kernel.
@@ -100 +99 @@
          */
         cp0_mask_all_int();
+
         /*
          * Unmask hardware clock interrupt.
          */
         cp0_unmask_int(TIMER_IRQ);
-
-        /*
-         * Start hardware clock.
-         */
-        cp0_compare_write(cp0_compare_value + cp0_count_read());
 
         console_init();