Changeset d701672 in mainline

Timestamp:

2016-09-20T08:49:48Z (8 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

38097a43

Parents:

b30846e

Message:

Fix cstyle

File:

• kernel/arch/arm32/src/mach/integratorcp/integratorcp.c (modified) (10 diffs)

kernel/arch/arm32/src/mach/integratorcp/integratorcp.c

@@ -55 +55 @@
 
 
-
-#define SDRAM_SIZE      (sdram[((*(uint32_t *)(ICP_CMCR+ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2)])
+#define SDRAM_SIZE \
+        sdram[(*(uint32_t *) (ICP_CMCR + ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2]
 
 static struct {
@@ -63 +63 @@
         pl011_uart_t uart;
 } icp;
-
-
 
 struct arm_machine_ops icp_machine_ops = {
@@ -98 +96 @@
 void icp_vga_init(void)
 {
-        *(uint32_t*)((char *)(icp.hw_map.cmcr)+0x14) = 0xA05F0000;
-        *(uint32_t*)((char *)(icp.hw_map.cmcr)+0x1C) = 0x12C11000;
-        *(uint32_t*)icp.hw_map.vga = 0x3F1F3F9C;
-        *(uint32_t*)((char *)(icp.hw_map.vga) + 0x4) = 0x080B61DF;
-        *(uint32_t*)((char *)(icp.hw_map.vga) + 0x8) = 0x067F3800;
-        *(uint32_t*)((char *)(icp.hw_map.vga) + 0x10) = ICP_FB;
-        *(uint32_t *)((char *)(icp.hw_map.vga) + 0x1C) = 0x182B;
-        *(uint32_t*)((char *)(icp.hw_map.cmcr)+0xC) = 0x33805000;
+        *(uint32_t *) ((char *)(icp.hw_map.cmcr) + 0x14) = 0xA05F0000;
+        *(uint32_t *) ((char *)(icp.hw_map.cmcr) + 0x1C) = 0x12C11000;
+        *(uint32_t *) icp.hw_map.vga = 0x3F1F3F9C;
+        *(uint32_t *) ((char *)(icp.hw_map.vga) + 0x4) = 0x080B61DF;
+        *(uint32_t *) ((char *)(icp.hw_map.vga) + 0x8) = 0x067F3800;
+        *(uint32_t *) ((char *)(icp.hw_map.vga) + 0x10) = ICP_FB;
+        *(uint32_t *) ((char *)(icp.hw_map.vga) + 0x1C) = 0x182B;
+        *(uint32_t *) ((char *)(icp.hw_map.cmcr) + 0xC) = 0x33805000;
         
 }
@@ -114 +112 @@
         return *((uint32_t *) icp.hw_map.irqc);
 }
-
 
 /** Masks interrupt.
@@ -173 +170 @@
 {
         icp_irqc_mask(ICP_TIMER_IRQ);
-        *((uint32_t*) icp.hw_map.rtc1_load) = frequency;
-        *((uint32_t*) icp.hw_map.rtc1_bgload) = frequency;
-        *((uint32_t*) icp.hw_map.rtc1_ctl) = ICP_RTC_CTL_VALUE;
+        *((uint32_t *) icp.hw_map.rtc1_load) = frequency;
+        *((uint32_t *) icp.hw_map.rtc1_bgload) = frequency;
+        *((uint32_t *) icp.hw_map.rtc1_ctl) = ICP_RTC_CTL_VALUE;
         icp_irqc_unmask(ICP_TIMER_IRQ);
 }
@@ -182 +179 @@
 {
         if (icp.hw_map.rtc1_intrstat) {
-                *((uint32_t*) icp.hw_map.rtc1_intrclr) = 1;
+                *((uint32_t *) icp.hw_map.rtc1_intrclr) = 1;
                 return IRQ_ACCEPT;
         } else
@@ -218 +215 @@
 }
 
-
 /** Starts timer.
  *
@@ -240 +236 @@
 
         if (hw_map_init_called) {
-                *size = (sdram[((*(uint32_t *)icp.hw_map.sdramcr &
-                    ICP_SDRAM_MASK) >> 2)]);
+                *size = sdram[(*(uint32_t *) icp.hw_map.sdramcr &
+                    ICP_SDRAM_MASK) >> 2];
         } else {
                 *size = SDRAM_SIZE;
@@ -325 +321 @@
 
         pl050_t *pl050 = malloc(sizeof(pl050_t), FRAME_ATOMIC);
-        pl050->status = (ioport8_t *)icp.hw_map.kbd_stat;
-        pl050->data = (ioport8_t *)icp.hw_map.kbd_data;
-        pl050->ctrl = (ioport8_t *)icp.hw_map.kbd_ctrl;
+        pl050->status = (ioport8_t *) icp.hw_map.kbd_stat;
+        pl050->data = (ioport8_t *) icp.hw_map.kbd_data;
+        pl050->ctrl = (ioport8_t *) icp.hw_map.kbd_ctrl;
                 
         pl050_instance_t *pl050_instance = pl050_init(pl050, ICP_KBD_IRQ);
@@ -347 +343 @@
         sysinfo_set_item_val("kbd", NULL, true);
         sysinfo_set_item_val("kbd.inr", NULL, ICP_KBD_IRQ);
-        sysinfo_set_item_val("kbd.address.physical", NULL,
-            ICP_KBD);
+        sysinfo_set_item_val("kbd.address.physical", NULL, ICP_KBD);
 
 #ifdef CONFIG_PL011_UART