Changes in kernel/arch/sparc64/src/sun4u/start.S [a52e2f4:d70ebffe] in mainline

File:

• kernel/arch/sparc64/src/sun4u/start.S (modified) (8 diffs)

kernel/arch/sparc64/src/sun4u/start.S

@@ -27 +27 @@
 #
 
-#include <abi/asmtool.h>
-
 #include <arch/arch.h>
 #include <arch/cpu.h>
@@ -78 +76 @@
  */
 
-SYMBOL(kernel_image_start)
+.global kernel_image_start
+kernel_image_start:
         mov BSP_FLAG, %l0
         and %o0, %l0, %l7                       ! l7 <= bootstrap processor?
@@ -397 +396 @@
 
 .align 8
-SYMBOL(physmem_base)    ! copy of the physical memory base address
+.global physmem_base            ! copy of the physical memory base address
+physmem_base:
         .quad 0
 
@@ -405 +405 @@
  * are meant to stay together, aligned on a 32B boundary.
  */
+.global fast_data_access_mmu_miss_data_hi
+.global end_of_identity 
+.global kernel_8k_tlb_data_template
+.global tlb_tag_access_context_mask
 
 .align 32 
@@ -410 +414 @@
  * This label is used by the fast_data_access_MMU_miss trap handler.
  */
-SYMBOL(fast_data_access_mmu_miss_data_hi)
+fast_data_access_mmu_miss_data_hi:
 /*
  * This variable is used by the fast_data_access_MMU_miss trap handler.
@@ -416 +420 @@
  * memory.
  */
-SYMBOL(end_of_identity)
+end_of_identity:
         .quad -1 
 /*
@@ -423 +427 @@
  * physical memory.
  */
-SYMBOL(kernel_8k_tlb_data_template)
+kernel_8k_tlb_data_template:
 #ifdef CONFIG_VIRT_IDX_DCACHE
         .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \
@@ -436 +440 @@
  * It allows us to save one precious instruction slot of this handler.
  */
-SYMBOL(tlb_tag_access_context_mask)
+tlb_tag_access_context_mask:
         .quad TLB_TAG_ACCESS_CONTEXT_MASK