Changes in kernel/arch/amd64/include/asm.h [f77e591d:d99c1d2] in mainline
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kernel/arch/amd64/include/asm.h
rf77e591d rd99c1d2 38 38 #include <config.h> 39 39 #include <typedefs.h> 40 #include <arch/cpu.h> 41 #include <trace.h> 40 41 extern void asm_delay_loop(uint32_t t); 42 extern void asm_fake_loop(uint32_t t); 42 43 43 44 /** Return base address of current stack. … … 48 49 * 49 50 */ 50 NO_TRACEstatic inline uintptr_t get_stack_base(void)51 static inline uintptr_t get_stack_base(void) 51 52 { 52 53 uintptr_t v; … … 55 56 "andq %%rsp, %[v]\n" 56 57 : [v] "=r" (v) 57 : "0" (~((uint64_t) STACK_SIZE -1))58 : "0" (~((uint64_t) STACK_SIZE-1)) 58 59 ); 59 60 … … 61 62 } 62 63 63 NO_TRACE static inline void cpu_sleep(void) 64 { 65 asm volatile ( 66 "hlt\n" 67 ); 68 } 69 70 NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void) 64 static inline void cpu_sleep(void) 65 { 66 asm volatile ("hlt\n"); 67 } 68 69 static inline void __attribute__((noreturn)) cpu_halt(void) 71 70 { 72 71 while (true) { … … 77 76 } 78 77 78 79 79 /** Byte from port 80 80 * … … 85 85 * 86 86 */ 87 NO_TRACEstatic inline uint8_t pio_read_8(ioport8_t *port)87 static inline uint8_t pio_read_8(ioport8_t *port) 88 88 { 89 89 uint8_t val; … … 106 106 * 107 107 */ 108 NO_TRACEstatic inline uint16_t pio_read_16(ioport16_t *port)108 static inline uint16_t pio_read_16(ioport16_t *port) 109 109 { 110 110 uint16_t val; … … 127 127 * 128 128 */ 129 NO_TRACEstatic inline uint32_t pio_read_32(ioport32_t *port)129 static inline uint32_t pio_read_32(ioport32_t *port) 130 130 { 131 131 uint32_t val; … … 148 148 * 149 149 */ 150 NO_TRACEstatic inline void pio_write_8(ioport8_t *port, uint8_t val)150 static inline void pio_write_8(ioport8_t *port, uint8_t val) 151 151 { 152 152 asm volatile ( 153 153 "outb %b[val], %w[port]\n" 154 :: [val] "a" (val), 155 [port] "d" (port) 154 :: [val] "a" (val), [port] "d" (port) 156 155 ); 157 156 } … … 165 164 * 166 165 */ 167 NO_TRACEstatic inline void pio_write_16(ioport16_t *port, uint16_t val)166 static inline void pio_write_16(ioport16_t *port, uint16_t val) 168 167 { 169 168 asm volatile ( 170 169 "outw %w[val], %w[port]\n" 171 :: [val] "a" (val), 172 [port] "d" (port) 170 :: [val] "a" (val), [port] "d" (port) 173 171 ); 174 172 } … … 182 180 * 183 181 */ 184 NO_TRACEstatic inline void pio_write_32(ioport32_t *port, uint32_t val)182 static inline void pio_write_32(ioport32_t *port, uint32_t val) 185 183 { 186 184 asm volatile ( 187 185 "outl %[val], %w[port]\n" 188 :: [val] "a" (val), 189 [port] "d" (port) 186 :: [val] "a" (val), [port] "d" (port) 190 187 ); 191 188 } 192 189 193 190 /** Swap Hidden part of GS register with visible one */ 194 NO_TRACE static inline void swapgs(void) 195 { 196 asm volatile ( 197 "swapgs" 198 ); 191 static inline void swapgs(void) 192 { 193 asm volatile("swapgs"); 199 194 } 200 195 … … 207 202 * 208 203 */ 209 NO_TRACEstatic inline ipl_t interrupts_enable(void) {204 static inline ipl_t interrupts_enable(void) { 210 205 ipl_t v; 211 206 … … 228 223 * 229 224 */ 230 NO_TRACEstatic inline ipl_t interrupts_disable(void) {225 static inline ipl_t interrupts_disable(void) { 231 226 ipl_t v; 232 227 … … 248 243 * 249 244 */ 250 NO_TRACEstatic inline void interrupts_restore(ipl_t ipl) {245 static inline void interrupts_restore(ipl_t ipl) { 251 246 asm volatile ( 252 247 "pushq %[ipl]\n" … … 263 258 * 264 259 */ 265 NO_TRACEstatic inline ipl_t interrupts_read(void) {260 static inline ipl_t interrupts_read(void) { 266 261 ipl_t v; 267 262 … … 275 270 } 276 271 277 /** Check interrupts state.278 *279 * @return True if interrupts are disabled.280 *281 */282 NO_TRACE static inline bool interrupts_disabled(void)283 {284 ipl_t v;285 286 asm volatile (287 "pushfq\n"288 "popq %[v]\n"289 : [v] "=r" (v)290 );291 292 return ((v & RFLAGS_IF) == 0);293 }294 295 272 /** Write to MSR */ 296 NO_TRACEstatic inline void write_msr(uint32_t msr, uint64_t value)273 static inline void write_msr(uint32_t msr, uint64_t value) 297 274 { 298 275 asm volatile ( … … 304 281 } 305 282 306 NO_TRACEstatic inline unative_t read_msr(uint32_t msr)283 static inline unative_t read_msr(uint32_t msr) 307 284 { 308 285 uint32_t ax, dx; … … 317 294 } 318 295 296 319 297 /** Enable local APIC 320 298 * … … 322 300 * 323 301 */ 324 NO_TRACEstatic inline void enable_l_apic_in_msr()302 static inline void enable_l_apic_in_msr() 325 303 { 326 304 asm volatile ( … … 330 308 "orl $(0xfee00000),%%eax\n" 331 309 "wrmsr\n" 332 ::: "%eax", "%ecx", "%edx" 333 ); 310 ::: "%eax","%ecx","%edx" 311 ); 312 } 313 314 static inline uintptr_t * get_ip() 315 { 316 uintptr_t *ip; 317 318 asm volatile ( 319 "mov %%rip, %[ip]" 320 : [ip] "=r" (ip) 321 ); 322 323 return ip; 334 324 } 335 325 … … 339 329 * 340 330 */ 341 NO_TRACEstatic inline void invlpg(uintptr_t addr)331 static inline void invlpg(uintptr_t addr) 342 332 { 343 333 asm volatile ( … … 352 342 * 353 343 */ 354 NO_TRACEstatic inline void gdtr_load(ptr_16_64_t *gdtr_reg)344 static inline void gdtr_load(ptr_16_64_t *gdtr_reg) 355 345 { 356 346 asm volatile ( … … 365 355 * 366 356 */ 367 NO_TRACEstatic inline void gdtr_store(ptr_16_64_t *gdtr_reg)357 static inline void gdtr_store(ptr_16_64_t *gdtr_reg) 368 358 { 369 359 asm volatile ( … … 378 368 * 379 369 */ 380 NO_TRACEstatic inline void idtr_load(ptr_16_64_t *idtr_reg)370 static inline void idtr_load(ptr_16_64_t *idtr_reg) 381 371 { 382 372 asm volatile ( … … 390 380 * 391 381 */ 392 NO_TRACEstatic inline void tr_load(uint16_t sel)382 static inline void tr_load(uint16_t sel) 393 383 { 394 384 asm volatile ( … … 398 388 } 399 389 400 #define GEN_READ_REG(reg) NO_TRACEstatic inline unative_t read_ ##reg (void) \390 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ 401 391 { \ 402 392 unative_t res; \ … … 408 398 } 409 399 410 #define GEN_WRITE_REG(reg) NO_TRACEstatic inline void write_ ##reg (unative_t regn) \400 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ 411 401 { \ 412 402 asm volatile ( \ … … 435 425 GEN_WRITE_REG(dr7) 436 426 437 extern void asm_delay_loop(uint32_t); 438 extern void asm_fake_loop(uint32_t); 439 440 extern uintptr_t int_0; 441 extern uintptr_t int_1; 442 extern uintptr_t int_2; 443 extern uintptr_t int_3; 444 extern uintptr_t int_4; 445 extern uintptr_t int_5; 446 extern uintptr_t int_6; 447 extern uintptr_t int_7; 448 extern uintptr_t int_8; 449 extern uintptr_t int_9; 450 extern uintptr_t int_10; 451 extern uintptr_t int_11; 452 extern uintptr_t int_12; 453 extern uintptr_t int_13; 454 extern uintptr_t int_14; 455 extern uintptr_t int_15; 456 extern uintptr_t int_16; 457 extern uintptr_t int_17; 458 extern uintptr_t int_18; 459 extern uintptr_t int_19; 460 extern uintptr_t int_20; 461 extern uintptr_t int_21; 462 extern uintptr_t int_22; 463 extern uintptr_t int_23; 464 extern uintptr_t int_24; 465 extern uintptr_t int_25; 466 extern uintptr_t int_26; 467 extern uintptr_t int_27; 468 extern uintptr_t int_28; 469 extern uintptr_t int_29; 470 extern uintptr_t int_30; 471 extern uintptr_t int_31; 472 extern uintptr_t int_32; 473 extern uintptr_t int_33; 474 extern uintptr_t int_34; 475 extern uintptr_t int_35; 476 extern uintptr_t int_36; 477 extern uintptr_t int_37; 478 extern uintptr_t int_38; 479 extern uintptr_t int_39; 480 extern uintptr_t int_40; 481 extern uintptr_t int_41; 482 extern uintptr_t int_42; 483 extern uintptr_t int_43; 484 extern uintptr_t int_44; 485 extern uintptr_t int_45; 486 extern uintptr_t int_46; 487 extern uintptr_t int_47; 488 extern uintptr_t int_48; 489 extern uintptr_t int_49; 490 extern uintptr_t int_50; 491 extern uintptr_t int_51; 492 extern uintptr_t int_52; 493 extern uintptr_t int_53; 494 extern uintptr_t int_54; 495 extern uintptr_t int_55; 496 extern uintptr_t int_56; 497 extern uintptr_t int_57; 498 extern uintptr_t int_58; 499 extern uintptr_t int_59; 500 extern uintptr_t int_60; 501 extern uintptr_t int_61; 502 extern uintptr_t int_62; 503 extern uintptr_t int_63; 427 extern size_t interrupt_handler_size; 428 extern void interrupt_handlers(void); 504 429 505 430 #endif
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