Changes in kernel/arch/ia32/include/interrupt.h [676afa2:d99c1d2] in mainline
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kernel/arch/ia32/include/interrupt.h
r676afa2 rd99c1d2 38 38 #include <typedefs.h> 39 39 #include <arch/pm.h> 40 #include <trace.h>41 40 42 #define IVT_ITEMS 43 #define IVT_FIRST 41 #define IVT_ITEMS IDT_ITEMS 42 #define IVT_FIRST 0 44 43 45 #define EXC_COUNT 46 #define IRQ_COUNT 44 #define EXC_COUNT 32 45 #define IRQ_COUNT 16 47 46 48 #define IVT_EXCBASE 49 #define IVT_IRQBASE 50 #define IVT_FREEBASE 47 #define IVT_EXCBASE 0 48 #define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT) 49 #define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT) 51 50 52 #define IRQ_CLK 53 #define IRQ_KBD 54 #define IRQ_PIC1 55 #define IRQ_PIC_SPUR 56 #define IRQ_MOUSE 57 #define IRQ_DP8390 51 #define IRQ_CLK 0 52 #define IRQ_KBD 1 53 #define IRQ_PIC1 2 54 #define IRQ_PIC_SPUR 7 55 #define IRQ_MOUSE 12 56 #define IRQ_DP8390 9 58 57 59 /* This one must have four least significant bits set to ones */60 #define VECTOR_APIC_SPUR 58 /* this one must have four least significant bits set to ones */ 59 #define VECTOR_APIC_SPUR (IVT_ITEMS - 1) 61 60 62 61 #if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS) … … 64 63 #endif 65 64 66 #define VECTOR_DEBUG 67 #define VECTOR_CLK 68 #define VECTOR_PIC_SPUR 69 #define VECTOR_SYSCALL 70 #define VECTOR_TLB_SHOOTDOWN_IPI 71 #define VECTOR_DEBUG_IPI 65 #define VECTOR_DEBUG 1 66 #define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK) 67 #define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR) 68 #define VECTOR_SYSCALL IVT_FREEBASE 69 #define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1) 70 #define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) 72 71 73 72 typedef struct istate { 74 /* 75 * The strange order of the GPRs is given by the requirement to use the 76 * istate structure for both regular interrupts and exceptions as well 77 * as for syscall handlers which use this order as an optimization. 78 */ 73 uint32_t eax; 74 uint32_t ecx; 79 75 uint32_t edx; 80 uint32_t ecx;81 uint32_t ebx;82 uint32_t esi;83 uint32_t edi;84 76 uint32_t ebp; 85 uint32_t eax; 86 87 uint32_t ebp_frame; /* imitation of frame pointer linkage */ 88 uint32_t eip_frame; /* imitation of return address linkage */ 89 77 90 78 uint32_t gs; 91 79 uint32_t fs; 92 80 uint32_t es; 93 81 uint32_t ds; 94 95 uint32_t error_word; /* real or fake error word */82 83 uint32_t error_word; 96 84 uint32_t eip; 97 85 uint32_t cs; 98 86 uint32_t eflags; 99 uint32_t esp; /* only if istate_t is from uspace */ 100 uint32_t ss; /* only if istate_t is from uspace */ 87 uint32_t stack[]; 101 88 } istate_t; 102 89 103 90 /** Return true if exception happened while in userspace */ 104 NO_TRACEstatic inline int istate_from_uspace(istate_t *istate)91 static inline int istate_from_uspace(istate_t *istate) 105 92 { 106 93 return !(istate->eip & 0x80000000); 107 94 } 108 95 109 NO_TRACE static inline void istate_set_retaddr(istate_t *istate, 110 uintptr_t retaddr) 96 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) 111 97 { 112 98 istate->eip = retaddr; 113 99 } 114 100 115 NO_TRACEstatic inline unative_t istate_get_pc(istate_t *istate)101 static inline unative_t istate_get_pc(istate_t *istate) 116 102 { 117 103 return istate->eip; 118 104 } 119 105 120 NO_TRACEstatic inline unative_t istate_get_fp(istate_t *istate)106 static inline unative_t istate_get_fp(istate_t *istate) 121 107 { 122 108 return istate->ebp; 123 109 } 124 110 125 extern void (* disable_irqs_function)(uint16_t );126 extern void (* enable_irqs_function)(uint16_t );111 extern void (* disable_irqs_function)(uint16_t irqmask); 112 extern void (* enable_irqs_function)(uint16_t irqmask); 127 113 extern void (* eoi_function)(void); 128 114 115 extern void decode_istate(istate_t *istate); 129 116 extern void interrupt_init(void); 130 extern void trap_virtual_enable_irqs(uint16_t );131 extern void trap_virtual_disable_irqs(uint16_t );117 extern void trap_virtual_enable_irqs(uint16_t irqmask); 118 extern void trap_virtual_disable_irqs(uint16_t irqmask); 132 119 133 120 #endif
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